Claims
- 1. A semiconductor memory comprising:
- a pair of data lines which are formed substantially in parallel to each other;
- a plurality of word lines, each of which is arranged so as to intersect with both of said data lines of said pair of data lines;
- a plurality of dynamic memory cells, each of which is coupled to one of said word lines and to one of said data lines;
- an amplifier, coupled to said pair of data lines, adapted to amplify a potential difference between said data lines so as to provide said data lines with a high-level potential and a low-level potential, respectively, wherein said amplifier includes a pair of N-channel MOS transistors and a pair of P-channel MOS transistors, wherein each transistor of said pair of N-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of N-channel MOS transistors, wherein a drain of one of said pair of N-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of N-channel MOS transistors is coupled to the other of said pair of data lines, wherein each transistor of said pair of P-channel MOS transistors has a gate cross-coupled to a drain of the other transistor of said pair of P-channel MOS transistors, and wherein a drain of one of said pair of P-channel MOS transistors is coupled to one of said pair of data lines and the drain of the other of said pair of P-channel MOS transistors is coupled to the other of said pair of data lines; and
- a precharging circuit adapted to set said data lines at a predetermined level when said plurality of dynamic memory cells are in a non-selected state, wherein said predetermined level is an intermediate level between said high-level potential and said low-level potential.
- 2. A semiconductor memory according to claim 1, further comprising:
- a first switching MOS transistor of N-channel type having a drain coupled to a source of each of said pair of N-channel MOS transistors and a source coupled to a first potential terminal; and
- a second switching MOS transistor of P-channel type having a drain coupled to a source of each of said pair of P-channel MOS transistors and a source coupled to a second potential terminal.
- 3. A semiconductor memory according to claim 2,
- wherein said precharging circuit includes a third switching MOS transistor having a source-drain path provided between said pair of data lines, and
- wherein said third switching MOS transistor is controlled so that said pair of data lines are electrically coupled to each other when said plurality of dynamic memory cells are in said non-selected state.
- 4. A semiconductor memory according to claim 3,
- wherein said first potential terminal has a potential level corresponding to said low-level potential, and
- wherein said second potential terminal has a potential level corresponding to said high-level potential.
- 5. A semiconductor memory according to claim 4, further comprising a control circuit adapted to supply control signals to a gate of said first switching MOS transistor and a gate of said second switching MOS transistor, respectively, so that operation of said pair of N-channel MOS transistors is started at a time different from the time when operation of said pair of P-channel MOS transistors is started.
- 6. A semiconductor memory according to claim 4, further comprising a fourth switching MOS transistor of N-channel type having a drain coupled to said source of each of said pair of N-channel MOS transistors and a source coupled to said first potential terminal, wherein said fourth switching MOS transistor is turned "on" at a time different from the time when said first switching MOS transistor is turned "on".
Priority Claims (1)
Number |
Date |
Country |
Kind |
56-70733 |
May 1981 |
JPX |
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Parent Case Info
This is a continuation of application Ser. No. 193,896, filed Feb. 9, 1994, now U.S. Pat. No. 5,365,478 which is a continuation of application Ser. No. 115,241, filed Aug. 18, 1993, which is a continuation of application Ser. No. 985,644, filed Dec. 7, 1992, which is a continuation of application Ser. No. 864,934, filed Apr. 7, 1992, now U.S. Pat. No. 5,170, 374 was a continuation of Ser. No. 07/515,345 filed Apr. 30, 1990, now U.S. Pat. No. 5,119,382 which is a continuation of Ser. No. 07/397,119 filed Aug. 22, 1989, which is a continuation of application Ser. No. 07/230,046 filed Aug. 9, 1988now U.S. Pat. No. 4,860,255 which is a continuation of Ser. No. 07/120,539 filed Nov. 13, 1987, now abandoned, which is a division of application Ser. No. 07/941,840 filed Dec. 15, 1986, now U.S. Pat. No. 4,709,353, which is a division of application Ser. No. 07/854,502 filed Apr. 22, 1986, now U.S. Pat. No. 4,646,267, which is a division of application Ser. No. 07/756,707 filed Jul. 19, 1985, now U.S. Pat. No. 4,592,022, which is a division of application Ser. No. 07/638,982 filed Aug. 8, 1984, now U.S. Pat. No. 4,539,658, which is a division of application Ser. No. 07/377,958 filed May 13, 1982, now U.S. Pat. No. 4,472,792.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
5383158 |
Ikegami |
Jan 1995 |
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Divisions (5)
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Number |
Date |
Country |
Parent |
941840 |
Dec 1986 |
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Parent |
854502 |
Apr 1986 |
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Parent |
756707 |
Jul 1985 |
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Parent |
638982 |
Aug 1984 |
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Parent |
377958 |
May 1982 |
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Continuations (8)
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Date |
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Parent |
193896 |
Feb 1994 |
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Parent |
115241 |
Aug 1993 |
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Parent |
985644 |
Dec 1992 |
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Parent |
864934 |
Apr 1992 |
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Parent |
414345 |
Apr 1990 |
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Parent |
397119 |
Aug 1989 |
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Parent |
230046 |
Aug 1988 |
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Parent |
120539 |
Nov 1987 |
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