Patent Application
20080088008
The embodiments of the present invention will be described with reference to the attached drawings, in which:
The present invention is described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in various different forms and should not be construed as being limited to the illustrated embodiments. Rather, these embodiments are provided as examples, to convey the concept of the invention to one skilled in the art. Accordingly, known processes, elements, and techniques are not described with respect to some of the embodiments of the present invention. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.
It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Throughout the drawings and written description, like reference numerals will be used to refer to like or similar elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the disclosed embodiments.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation of above and below. Likewise, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors should be interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “includes” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having meanings that consistent with the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so provided.
Referring to
The semiconductor chip 110 may have a substantially rectangular shape. Thus, the semiconductor chip 110 has two long sides opposite to each other, and two short sides opposite to each other and substantially perpendicular to the two long sides. The ends of each of the two short sides are respectively connected to ends of the two long sides.
The first outer connection pads 120 are arranged along first edges of the semiconductor chip 110 in a first direction, which is substantially parallel with the long sides of the semiconductor chip 110. The second outer connection pads 122 are arranged along second edges of the semiconductor chip in a second direction, which is substantially perpendicular to the first direction. In other words, the second direction is substantially parallel with the short sides of the semiconductor chip 110. As a result, the first and the second outer connection pads 120 and 122 are respectively arranged along the first and the second edges of the semiconductor chip 110 to generally form a rectangular frame shape.
The first outer connection leads 130 are electrically connected to the first outer connection pads 120, respectively. In the depicted embodiment, the first outer connection leads 130 may be arranged along the first direction and extend parallel to one another in the second direction. Likewise, the second outer connection leads 132 are electrically connected to the second outer connection pads 122, respectively. In the depicted embodiment, the second outer connection leads 132 may be arranged along the second direction and extend parallel to one another in the first direction.
The power pads 124 are arranged on the semiconductor chip 110 between the first outer connection pads 120. In the depicted embodiment, the power pads 124 are arranged in the second direction, such that an end power pad 124 is positioned closest to the first edge of the semiconductor chip 110 and the remaining power pads 124 extend in the second direction away from the first edge. That is, the direction in which the power pads 124 are arranged may be substantially perpendicular to the direction of the first outer connection pads 120. In an embodiment, the end power pad 124 may also be substantially aligned with the outer connection pads 120 positioned along the first edge.
The single power lead 134 is electrically connected to the power pads 124. Because the power pads 124 are aligned in the second direction, the power lead 134 extends across the power pads 124 also in the second direction.
The ground pads 126 are arranged on the semiconductor chip 110 between the first outer connection pads 120. In the depicted embodiment, the ground pads 126 are arranged in the second direction, such that an end ground pad 126 is positioned along the first edge of the semiconductor chip 110 and the remaining ground pads 126 extend in the second direction away from the first edge. That is, the direction in which the ground pads 124 are arranged may be substantially perpendicular to the direction of the first outer connection pads 120. In an embodiment, the first ground pad 126 may also be substantially aligned with the outer connection pads 120 positioned along the first edge.
The single ground lead 136 is electrically connected to the ground pads 126. Because the ground pads 126 are aligned along the second direction, the ground lead 136 extends across the ground pads 126 also in the second direction.
The power pads 124 and the ground pads 126 are positioned along the second direction to provide sufficient space for the first outer connection pads 120 to be widely spaced along the first direction on the semiconductor chip 110. Therefore, a pitch between the first outer connection pads 120 may be sufficiently widened. As a result, for example, probes used for testing the semiconductor package 100 may accurately contact each of the first outer connection pads 120, so that the semiconductor package 100 may be easily and efficiently tested. Further, since circuit patterns of the semiconductor package 100 and the probes may have wider pitches, the manufacturing costs of the semiconductor package 100 and the probes may be reduced.
Further, the additional space on the semiconductor chip 110 enables the first outer connection leads 130 and the power lead 134 to be sufficiently wide. In particular, the power lead 134, which transmits power to the semiconductor chip 110, may have a width d2, which is greater than a width d1 of each first outer connection lead 130. Therefore, the power may be rapidly and efficiently transmitted through the power lead 134, enhancing the capabilities of the semiconductor package 100.
According to the first exemplary embodiment, the direction in which the power pads 124 and the ground pads 126 are aligned may be substantially perpendicular to the direction in which the first outer connection pads 120 are aligned. Therefore, the space in which the first outer connection pads 120 are positioned in the first direction may be guaranteed on the semiconductor chip 110. As a result, the first outer connection pads 120 may have a wide pitch.
The semiconductor package 100a of the depicted embodiment substantially includes the elements of the semiconductor package 100 of the First Example Embodiment, except that additional second power pads 124a, second ground pads 126a, a second power lead 134a and a second ground lead 136a are included. Therefore, the same reference numerals refer to the same elements depicted in
Referring to
Further, the second power lead 134a extends in the first direction, and is electrically connected to the second power pads 124a. The second ground lead 136a also extends in the first direction, and is electrically connected to the second ground pads 126a.
According to the depicted embodiment, the second power pads 124a and the second ground pads 126a are arranged in a direction substantially perpendicular to the direction in which the second outer connection pads 122 are arranged, extending from the second edge of the semiconductor device 110. Therefore, the semiconductor chip 110 may provide sufficient space for the second outer connection pads 122 to be arranged in the second direction. As a result, the second outer connection pads 122 may have a wider pitch.
In the exemplary embodiments, the semiconductor package may be a COF package, for example. Alternatively, the embodiments may be included in other types of semiconductor packages having connection pads, power pads and ground pads, without departing from the spirit and scope of the present invention.
According to embodiments of the present invention, power pads and ground pads are generally arranged substantially perpendicular to the direction in which outer connection pads are arranged, so that the pitch between the outer connection pads may be widened. Also, probes may make better contact with the outer connection pads due to the increased width. As a result, the semiconductor chip may be readily tested using the probes.
Further, costs of manufacturing the semiconductor package and the probes may be reduced. Furthermore, the current transmission speed through the wider leads may be greater, improving the capabilities and capacities of semiconductor package.
While the present invention has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. Therefore, it should be understood that the above embodiments are not limiting, but illustrative.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2006-0099112 | Oct 2006 | KR | national |
