Patent Application
20160109512
This application claims under 35 U.S.C. §119 priority to and the benefit of Korean Patent Application No. 10-2014-0140163, filed on Oct. 16, 2014, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
The inventive concepts relate to a semiconductor package test blade and a semiconductor package test apparatus, which are connected to a semiconductor package test handler apparatus, and more particularly, to a semiconductor package test blade and a semiconductor package test apparatus, which may prevent damage to a semiconductor package during a pass/fail test on semiconductor packages.
The development of a semiconductor package has progressed to reduce power consumption and increase operating speed. A method of performing a pass/fail test on the semiconductor package includes fixing a socket board on which a socket is mounted, by using a socket board fixing jig, and determining whether the semiconductor package is operational or defective by an electrical contact of the socket mounted on the socket board with the semiconductor package. The above-described pass/fail test on the semiconductor package may be performed by using a test handler including a pusher. Specifically, the semiconductor package may be pressed against the socket by using the pusher.
The inventive concepts provides a semiconductor package test blade and a semiconductor package test apparatus, which may prevent damage to semiconductor packages during a pass/fail test on semiconductor packages.
According to an aspect of the inventive concepts, a semiconductor package test blade may include: a blade body formed at a lower end portion of a pusher for testing a semiconductor package, the blade body having a first surface contacting the semiconductor package and a groove dented upward from the first surface to provide a second surface at a higher level than the first surface and opposite to the first surface, a vacuum suction picker configured to penetrate a central portion of the blade body and suck and pick up the semiconductor package by using a vacuum, and a flexible silicone layer filling the groove and being in contact with a second surface of the blade body. The second surface of the blade body may serve as a bottom surface of the groove. A bottom surface of the flexible silicone layer is at substantially the same level as the first surface of the blade body.
In some embodiments, the flexible silicone layer may comprise flexible silicone having a hardness of 1 to 10.
In some embodiments, the flexible silicone layer may comprise flexible silicone, or flexible silicone rubber.
In some embodiments, the flexible silicone layer may have a smaller planar area than a planar area of the blade body.
In some embodiments, the bottom side of the vacuum suction picker and the bottom surface of the flexible silicone layer may be in contact with a top surface of the semiconductor package.
In some embodiments, a sum of a planar area the flexible silicone layer and a planar area of the vacuum suction picker may be greater than a planar area of a semiconductor chip included in the semiconductor package to cover the semiconductor chip.
In some embodiments, the first surface of the blade body may be disposed in an outward direction relative to the second surface of the blade body.
In some embodiments, a bottom side of the vacuum suction picker may have a circular cross-sectional shape. A bottom surface of the flexible silicone layer may have a concentric sectional shape with the vacuum suction picker.
In some embodiments, a bottom side of the vacuum suction picker may have a circular cross-sectional shape. A bottom surface of the flexible silicone layer may have a squared sectional shape to surround the vacuum suction picker.
According to another aspect of the inventive concepts, a semiconductor package test apparatus may include: a plurality of test blades disposed in a row apart from one another, each test blade including a vacuum suction picker configured to suck and pick up a semiconductor package, a pusher block connected to the plurality of test blades and including a vacuum path communicate with each vacuum suction picker, and flexible silicone layers each on a first surface of each of the plurality of test blades, which are in contact with the semiconductor package.
In some embodiments, the semiconductor package test apparatus may further include protrusions at outer portions of the first surfaces of the plurality of test blades.
In some embodiments, bottom surfaces of the protrusions may be at substantially the same level as a bottom surface of the flexible silicone layer.
In some embodiments, the pusher block may be connected to a test handler and be in contact with second surfaces of the plurality of test blades opposite to the first surfaces thereof.
In some embodiments, the test blades may include at least one array including eight (8) test blades arranged in a row.
In some embodiments, the flexible silicone layer comprises flexible silicone having a hardness of 1 to 10.
According to another aspect of the inventive concepts, a semiconductor package test blade may include: a vacuum suction unit configured to suck and pick up a semiconductor package, a body unit configured to surround of the vacuum suction unit, wherein a groove is formed to a predetermined depth in a surface of the body unit, which is in contact with the semiconductor package, and a buffer unit configured to fill the groove and formed of a flexible material.
In some embodiments, the flexible silicone layer may be formed of flexible silicone having a hardness of 1 to 10.
In some embodiments, the vacuum suction unit may be disposed to the center of the body unit, and the silicone layer may be symmetrically formed with respect to the vacuum suction unit.
In some embodiments, the vacuum suction unit may be positioned in the center of the body unit, and the flexible silicone layer may be formed as a donut type around the vacuum suction unit.
In some embodiments, a lowermost surface of the body unit may be at substantially a same level as a lowermost surface of the flexible silicone layer.
Example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
The inventive concepts will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the inventive concepts are shown. The inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concepts to those skilled in the art. In the drawings, the sizes of layers and regions may be exaggerated for clarity.
It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Meanwhile, spatially relative terms, such as “between” and “directly between” or “adjacent to” and “directly adjacent to” and the like, which are used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures, should be interpreted similarly.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.
As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Spatially relative terms, such as “top end,” “bottom end,” “top surface,” “bottom surface,” “upper,” “lower” and the like, may be used herein for ease of description to, describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs.
Referring to
The semiconductor package test handler 10 may include the loading tray 1, the soaking chamber 2, the input shuttle 3, the test chamber T, the test sockets 4, the output shuttle 5, the unloading buffer 6, and the unloading tray 7.
A plurality of semiconductor packages to be tested may be contained in the loading tray 1. The loading tray 1 may be a transporting/handling tool in which the semiconductor packages are contained in a matrix shape. The loading tray 1 may be categorized as either a customer tray used to transfer semiconductor packages from user, or a test tray used only in a handler to connect the semiconductor packages with a tester. The loading tray 1 may be connected to the first transfer device and transferred to the soaking chamber 2 (A1).
In the soaking chamber 2, a process of aging the test tray transferred from the loading tray 1 may be performed under predetermined temperature conditions for a predetermined amount of time. The soaking chamber 2 may be used to test electrical performance of semiconductor packages at a high temperature or at a low temperature. The soaking chamber 2 may include a hot plate configured to heat the semiconductor packages at a high temperature. The semiconductor packages, which have passed the soaking chamber 2, may be connected to a second transfer device and transferred to the input shuttle 3 (A2).
The semiconductor packages contained in the input shuttle 3 may be transferred to a test chamber T in which a pass/fail test is performed (A3). For example, the input shuttle 3 containing semiconductor packages therein may be transferred to a test chamber T. The test chamber T may include test sockets 4. 16 semiconductor packages contained in the input shuttle 3 may be arranged in two arrays, each of which includes 8 semiconductor packages. However, the number of semiconductor packages that may be contained in the input shuttle 3 is not limited to 16, and at least one semiconductor package may be contained in the input shuttle 3. The semiconductor packages contained in the input shuttle 3 may be mounted on the test sockets 4 by using the pusher connected to the semiconductor package test handler 10 (A4). In the test sockets 4, a pass/fail test including an electrical performance test may be performed on the semiconductor packages (A5). In some embodiments, the test sockets 4 may be configured to perform the pass/fail test on a total of 16 semiconductor packages at one time. However, the number of semiconductor packages on which the pass/fail test is performed at one time in the test sockets 4 is not limited to 16. The test sockets 4 may be connected to a test head configured to perform the pass/fail test on the semiconductor packages. The semiconductor packages on which the pass/fail test has been performed in the test sockets 4 may be transferred to the output shuttle 5 and discharged out of the test chamber T (A6). For example, the output shuttle 5 containing semiconductor packages therein may be transferred out of the test chamber T.
The semiconductor packages contained in the output shuttle 5 may be transferred by the third transfer device to the unloading buffer 6 (A7). Similar to the input shuttle 3, 16 semiconductor packages may be contained in the output shuttle 5. However, the number of semiconductor packages that may be contained in the output shuttle 5 is not limited to 16. The unloading buffer 6 may perform a process of aging the semiconductor packages on which the pass/fail test is completely performed, at room temperature for a predetermined amount of time.
The semiconductor packages, which have passed the unloading buffer 6, may be transferred to the unloading tray 7 by the fourth transfer device (A8).
In some embodiments, the above-described operation A4 of mounting the semiconductor packages on the test sockets 4 by using the pusher may include sucking and picking up the semiconductor packages in vacuum by using the pusher connected to the semiconductor package test handler 10, and putting the semiconductor packages down on the test sockets 4. A test blade (refer to 100 in
Referring to
The test blade 100 may include a vacuum suction picker 110, a blade body 120 formed to surround the vacuum suction picker 110, a flexible silicone layer 130 formed on a surface of the blade body 120, which may be in contact with a semiconductor package 1000, The test blade 100 may be formed at the bottom end portion of the pusher block 200. In some embodiments, the test blade 100 may comprise a pusher, which may apply pressure to a top surface of the semiconductor package 1000 and mount the semiconductor package 1000 on the socket structure 300.
In some embodiments, the blade body 120 may have, for example, a hexahedral shape. However, the blade body 120 is not limited thereto and may have various shapes including a cylindrical shape or a polygonal shape. A planar area of the test blade 100 (e.g., a planar area of a bottom surface of the test blade 100) may be greater than a planar area of the top surface of the semiconductor package 1000 and substantially equal to a planar area of the socket substrate 320. The bottom surface of the blade body 120 may be formed at a planar level without a step difference. The blade body 120 may be formed of a metal material, such as aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), tin (Sn), silver (Ag), or gold (Au). In an example embodiment of the inventive concept, the blade body 120 may be formed of aluminum.
The vacuum suction picker 110 may be formed to penetrate a central portion of the blade body 120. The vacuum suction picker 110 may include the vacuum path (refer to 112 in
The flexible silicone layer 130 may be formed on the bottom surface of the blade body 120. The flexible silicone layer 130 may be formed around the vacuum suction picker 110 to surround the vacuum suction picker 110. The flexible silicone layer 130 may have a concentric sectional shape with the vacuum suction picker 110. For example, the flexible silicone layer 130 may have a donut shape to surround the vacuum suction picker 110.
In some embodiments, a planar area of the flexible silicone layer 130 may be smaller than the planar area of the semiconductor package 1000. A sum of planar areas of the flexible silicone layer 130 and the vacuum suction picker 110 may be greater than a planar area of a semiconductor chip 1100 included in the semiconductor package 1000. The flexible silicone layer 130 may be brought into contact with the top surface of the semiconductor package 1000 and/or the top surface of the semiconductor chip 1100 by the pusher block 200 so that the semiconductor package 1000 may be in contact with the socket structure 300. In some embodiments, the flexible silicone layer 130 may cover the top surface of the semiconductor chip 1100 except for a portion corresponding to the vacuum suction picker 110.
The flexible silicone layer 130 may be formed of a flexible material. For example, the flexible silicone layer 130 may be formed of flexible silicone, flexible silicone rubber. In some embodiments, the flexible silicone layer 130 may be formed of any one of flexible materials including polyurethane, polymer, synthetic resin. In other embodiments, the flexible silicone layer 130 may be formed of flexible silicone having a hardness of 1 to 10.
The pusher block 200 may be connected to a top surface of the test blade 100. The pusher block 200 may be connected to the semiconductor package test handler 10 and move upward and downward by a motor included in the semiconductor package test handler 10. As the pusher block 200 moves upward and downward, the test blade 100 also may move upward and downward. The test blade 100 may be brought into contact with the semiconductor package 1000 so that the semiconductor package 1000 may be mounted on the socket structure 300.
The socket structure 300 may include pogo-pins 310, a socket substrate 320, a socket body unit 330, and a test board 340. The socket body unit 330 may have a shape corresponding to an external shape of the test blade 100. That is, when the test blade 100 is moved downward by the pusher block 200 and brought into contact with the socket structure 300, the socket body unit 330 may surround at least a portion of outer side surfaces of the test blade 100 (refer to
The semiconductor package 1000 may be mounted on the socket structure 300. The semiconductor package 1000 may be pressed against the socket structure 300 by the test blade 100 connected to the pusher block 200. The semiconductor package 1000 may include a semiconductor chip 1100, a substrate 1200, a molding member 1300, and an external connection member 1400. The semiconductor package 1000 will be described in detail below with reference to
Referring to
The bottom surface of the blade body 120, and a bottom surface of the flexible silicone layer 130 may be at substantially the same level, which may be in contact with the semiconductor package 1000, may be flattened without causing a step difference, which will be described in detail with reference to
The semiconductor package 1000 may include a semiconductor chip 1100, a substrate 1200, a molding member 1300, and external connection members 1400. The substrate 1200 may include an upper layer 1210, a body layer 1220, a lower layer 1230, upper pads 1240, and lower pads 1250. The semiconductor chip 1100 may be mounted on the substrate 1200. The semiconductor chip 1100 may include a semiconductor device 1110 and connection terminals 1120. The semiconductor chip 1100 may be a microprocessor (MP). a central processing unit (CPU), a controller, an application specific integrated circuit (ASIC), or an application processor (AP) used for a mobile phone or a smartphone. The semiconductor chip 1100 may be a memory chip such as a DRAM chip, a FLASH memory chip or a MRAM chip. A top surface of the semiconductor chip 1100 may not be covered with the molding member 1300 and may be exposed. In some embodiments, the top surface of the semiconductor chip 1100 may be covered with the molding member 1300. The external connection members 1400 may be electrically and/or physically connected to the lower pads 1250 of the substrate 1200. The lower pads 1250 may be connected to the upper pads 1240 through the body layer 1220. As a result, the external connection members 1400 may be electrically connected to the semiconductor chip 1100.
When the pusher block 200 moves downward and the test blade 100 applies pressure due to the downward movement of the pusher block 200, the semiconductor package 1000 may be in contact with and mounted on the socket structure 300. The external connection members 1400 of the semiconductor package 1000 may be electrically and/or physically connected to the pogo-pins 310 of the socket structure 300. By electrically connecting the pogo-pins 310 with the semiconductor chip 1100, the socket structure 300 may test electrical performance and performance characteristics (e.g., radio-frequency (RF) signals and audio signals) of the semiconductor package 1000 and perform a pass/fail test on the semiconductor package 1000.
During the above-described operation of performing the pass/fail test on the semiconductor package 1000, the pusher block 200 may move downward and the test blade 100 may apply pressure to the top surface of the semiconductor package 1000. Therefore, when the semiconductor package 1000 is mounted on the socket structure 300 in contact with the socket structure 300, the semiconductor package 1000 may be damaged or broken.
For example, when foreign materials flow between the bottom surface of the test blade 100 and the top surface of the semiconductor package 1000, the foreign materials may apply pressure to the semiconductor package 1000 so that the semiconductor package 1000 may become damaged. In particular, as shown in
Referring to
A flexible silicone layer 130 may fill the groove G and contact the second surface S2. The flexible silicone layer 130 may be symmetrically formed with respect to the vacuum suction picker 110. A level S3 of a lowermost surface (or a bottom surface) of the flexible silicone layer 130 may be substantially the same as the level of the first surface S1. In other words, a bottom surface of the test blade 100 (i.e., the first surface S1 of the blade body 120, the lowermost surface S3 of the flexible silicone layer 130 may be at substantially the same level. Accordingly, the bottom surface of the test blade 100, which is in contact with a top surface of a semiconductor package 1000, may be flattened without causing a step difference.
Referring to
Referring to
The test blade 102 may include a vacuum suction picker 110, a blade body 122 formed to surround a side surface portion of the vacuum suction picker 112, and a flexible silicone layer 132 formed on a surface of the blade body 122, which is in contact with a semiconductor package 1000. The test blade 102 may be formed at a lower end portion of the pusher block 200. The test blade 102 may be a pusher, which may apply pressure to a top surface of the semiconductor package 1000 and mount the semiconductor package 1000 on the socket structure 300.
The blade body 122 may have a hexahedral shape. A planar area of the test blade 102 may be greater than a planar area of the top surface of semiconductor package 1000, and substantially equal to a planar area of a socket substrate 320. The blade body 122 may be formed of, for example, aluminum (Al). In some embodiments, the blade body 122 may be formed of copper (Cu), nickel (Ni), tungsten (W), tin (Sn), silver (Ag), or gold (Au).
A vacuum suction picker 112 may be formed in a central portion of the blade body 122 to penetrate the blade body 122. Since the vacuum suction picker 112 is formed in the same shape as the vacuum suction picker 110 shown in
A flexible silicone layer 132 may be formed on a bottom surface of the blade body 122. The flexible silicone layer 132 may be formed around the vacuum suction picker 112 to surround the vacuum suction picker 110. A bottom surface of the flexible silicone layer 132 may have a squared sectional shape to surround the vacuum suction picker 112. The flexible silicone layer 132 may not cover the entire bottom surface of the blade body 122 to expose a portion of the bottom surface of the blade body 122. The exposed portion of the bottom surface of the blade body 122 may be disposed outward relative to the flexible silicone layer 132.
In some embodiments, a planar area of the flexible silicone layer 132 may be smaller than a planar area of the semiconductor package 1000. A sum of planar areas of the flexible silicone layer 132 and the vacuum suction picker 112 may be greater than a planar area of the semiconductor chip 1100. The flexible silicone layer 132 may cover the top surface of the semiconductor chip.
The flexible silicone layer 132 may be formed of a flexible material. For example, the flexible silicone layer 132 may be formed of flexible silicone. Since the flexible silicone layer 132 is formed of the same material as the flexible silicone layer 130 shown in
Referring to
The plurality of test blades 100-1 to 100-8 may include 8 test blades, namely, first to eighth test blades 100-1 to 100-8. However, the number of test blades 100-1 to 100-8 is not limited to 8, and at least one test blade may be provided. The plurality of test blades 100-1 to 100-8 may be disposed in a row and form an array. Each of the plurality of test blades 100-1 to 100-8 may be the same as the test blade 100 shown in
A top surface of each of the plurality of test blades 100-1 to 100-8 may be connected to a lower end portion of the pusher block 202. The plurality of test blades 100-1 to 100-8 may be connected to one another by the pusher block 202. The pusher block 202 may be connected to the semiconductor package test handler 10b. The pusher block 202 may apply pressure to the plurality of test blades 100-1 to 100-8 so that a plurality of semiconductor packages 1000-1 to 1000-8 may be mounted on a plurality of socket structures 300-1 to 300-8, respectively.
A vacuum path 210 may be formed in the pusher block 202 and communicate with a plurality of vacuum suction pickers 120-1 to 120-8. Vacuum generated by the semiconductor package test handler 10b) may be transmitted to the plurality of vacuum suction pickers 120-1 to 120-8, which may communicate with the vacuum path 210. Thus, the plurality of vacuum suction pickers 120-1 to 120-8 may suck and pick up the plurality of semiconductor package 1000-1 to 1000-8, respectively.
The plurality of socket structures 300-1 to 300-8 may include 8 socket structures, namely, first to eighth socket structures 300-1 to 300-8, which may correspond to the plurality of test blades 100-1 to 100-8. The first socket structure 300-1 may correspond to the first test blade 100-1, the second socket structure 300-2 may correspond to the second test blade 100-2, and an n-th socket structure may correspond to an n-th test blade. The plurality of socket structures 300-1 to 300-8 may be connected to a test board 342.
The semiconductor package test handler 10b may include the plurality of test blades 100-1 to 100-8 and the pusher block 202 connected to the plurality of test blades 100-1 to 100-8 so that the plurality of semiconductor packages 1000-1 to 1000-8 may be simultaneously mounted on the plurality of socket structures 300-1 to 300-8. Similar to the test blade 100 shown in
Referring to
The plurality of test blades 100-1 to 100-16 may include a first array including first to eighth test blades 100-1 to 100-8 and a second array including ninth to sixteenth test blades 100-9 to 100-16. However, the plurality of test blades 100-1 to 100-16 are not limited two arrays, each of which includes 8 test blades. For example, the plurality of test blades 100-1 to 100-16 may include a plurality of arrays, each of which includes at least one test blade. Each of the plurality of test blades 100-1 to 100-16 may be the same as the test blade 100 shown in
The semiconductor package test handler 10c may include 2 arrays, each of which may include 8 test blades, and apply pressure to 16 semiconductor packages and simultaneously mount the 16 semiconductor packages on socket structures. The 16 test blades 100-1 to 100-16 may correspond to 16 test sockets 4 that may be arranged in two columns, each of which includes 8 test sockets 4, as shown in
Referring to
The plurality of test blades 102-1 to 102-16 may include a first array including first to eighth test blades 102-1 to 102-8 and a second array including ninth to sixteenth test blades 102-9 to 102-16. Each of the plurality of test blades 102-1 to 102-16 may be the same as the test blade 102 shown in
The semiconductor package test handler 10d shown in
While the inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2014-0140163 | Oct 2014 | KR | national |
