SEMICONDUCTOR PACKAGE

TECHNICAL FIELD

The present disclosure relates to a semiconductor package that can be used for, for example, a dual inline ceramic package, a quand flat package, a ball grid alley suitable for high integration with high terminal density, and the like, and particularly relates to a semiconductor package including an inner lead capable of wiring connection with a semiconductor chip having a large number of high-density terminals.

BACKGROUND ART

Recently, semiconductor devices have been used for various applications in a wide range of fields along with miniaturization and high integration of electronic circuits, terminals, and the like. For this reason, various packages for semiconductor chip mounting corresponding to downsizing, thinning, cost reduction, increase in pins, and the like have been developed.

The package used for these semiconductor devices, for example, the frame is dedicated for each product application, and a wide variety of packages are provided. Then, in a case where the specification of the product is changed or the product is redesigned, for example, the terminal position of the semiconductor chip is moved or the bonding position of the wire for wiring is changed without changing the frame itself (see, for example, Patent Document 1).

In the above-described semiconductor device, since a large number of wirings are provided, when the arrangement of the connection wirings is changed, for example, in the case of performing cross bonding or the like in which wires are connected in a crossed state, the bonding wire length becomes long, and thus there is a problem that the wires are in contact with each other or in contact with the semiconductor chip.

Therefore, there has been proposed a semiconductor device capable of changing a terminal position and the number by arranging inner leads side by side along a terminal of a semiconductor chip (see, for example, Patent Document 2).

CITATION LIST
Patent Document

- Patent Document 1: Japanese Patent Application Laid-Open No. 2000-77595
- Patent Document 2: Japanese Patent Application Laid-Open No. 2005-243694

SUMMARY OF THE INVENTION
Problems to be Solved by the Invention

In the semiconductor device described in Patent Document 2, as seen in the last embodiment, at the time of connecting the terminal on the semiconductor chip side and the inner lead, the degree of freedom in wiring from the terminal to the inner lead is increased by a certain extra length secured in the inner lead.

However, since the outer lead and the inner lead are configured to be fixed in a predetermined 1:1 correspondence relationship, the degree of freedom in wiring is narrowed in that respect. Therefore, for example, the configuration of Patent Document 2 is difficult to cope with a semiconductor chip in which a large number of terminals are provided in a matrix form at high density.

In addition, in the structure of Patent Document 2, a portion (bed portion) on which a semiconductor chip is mounted needs to be laid out before resin sealing.

An object of the present disclosure is to provide a semiconductor package that increases the degree of freedom of wiring arrangement and enables a wiring layout of various bonding wires that can cope with a case where a semiconductor chip to be mounted has a high-density terminal.

Solutions to Problems

The present disclosure has been made to achieve the above object, and a first aspect thereof is a semiconductor package including: a package main body portion; a bed portion which is provided on a center side of the package main body portion and on which a semiconductor chip is mounted; and an inner lead portion formed in a plurality of turns to surround a periphery of an outer edge side of the bed portion, the inner lead portion including a plurality of inner leads for establishing connection with the semiconductor chip.

In the first aspect, a plurality of the inner leads may be disposed in a spiral shape to surround a periphery of the semiconductor chip.

Further, in the first aspect, each of the inner leads has an island portion bulging laterally with respect to a wiring direction at a plurality of locations.

Further, in the first aspect, each of the inner leads is arranged side by side in a rectangular shape in a plurality of turns around four sides of outer edge sides of the bed portion having a substantially rectangular shape, and

- each of the inner leads has a configuration in which an entire length in each winding is:
  - formed over an entire of the four outer edge sides of the bed portion;
  - formed over three sides of the outer edge sides of the bed portion;
  - formed over two sides of the outer edge sides of the bed portion; or
  - formed in units of each side of the outer edge sides of the bed portion.

Furthermore, in the first embodiment, the island portion may have any one of a circular shape, an elliptical shape, a rhombus shape, and a rectangular shape.

Further, in the first embodiment, the package main body portion is constituted by ceramic.

A semiconductor package according to the present disclosure includes: a bed portion on which a semiconductor chip disposed on a center side of a package main body is mounted; and an inner lead portion formed in a plurality of turns so as to surround a periphery of an outer edge side of the bed portion, the inner lead portion including a plurality of inner leads for establishing connection with the semiconductor chip. Therefore, when wiring connection is performed from the semiconductor chip to the inner lead portion, wiring connection can be freely performed from the semiconductor chip toward the inner lead portion in each direction without any limitation on the inner lead portion from any direction and any place in the periphery of the outer edge portion of the bed portion.

In addition, similarly, in a case where the wiring is drawn out from the inner lead portion to the outer lead or the like outside, the wiring can be drawn out from any direction and any place of the inner lead portion. Therefore, even when terminals are formed at high density on the semiconductor chip mounted on the bed portion, wiring connection and wiring drawing can be performed corresponding to these terminals.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A is a schematic plan view illustrating a semiconductor package according to a first embodiment of the present disclosure, and FIG. 1B is a schematic cross-sectional view taken along line I-I of FIG. 1A.

FIG. 2 is an explanatory diagram illustrating a wiring area in a standard layout of a semiconductor chip and an inner lead portion in the semiconductor package illustrated in FIG. 1.

FIG. 3 is a schematic plan view illustrating a partial enlargement in the semiconductor package illustrated in FIG. 1.

FIG. 4 is an explanatory diagram illustrating a specific connection state of bonding wires in the semiconductor package illustrated in FIG. 1.

FIG. 5 is an explanatory diagram illustrating arrangements of inner lead portions of various configuration examples according to the present embodiment.

FIG. 6 is an explanatory diagram illustrating layouts of inner leads at a corner portion in an inner lead portion of various configuration examples according to the present embodiment.

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, modes for carrying out technology of the present disclosure (hereinafter described as “embodiments”) will be described in detail with reference to the drawings. The technology of the present disclosure is not limited to that of each embodiment, and various numerical values, materials, and the like in each embodiment are examples. In the following description, the same reference numerals are used for the same elements or elements having the same functions, and redundant description will be omitted. Note that the description is given in the following order.

1. Semiconductor Package According to Embodiment of Present Disclosure

1-1. First Configuration Example . . . Installation of I-Shaped Inner Lead Portion at Four Locations

1-2. Second Configuration Example . . . Installation of U-Shaped Inner Lead Portion at One Location

1-3. Third Configuration Example . . . Installation of L-Shaped Inner Lead Portion at Two Locations

1-4. Fourth configuration example . . . Installation of Inner Lead Portions in Which I-Shaped Parts Form Pair at Four Locations

<1. Ceramic Package Structure of Semiconductor According to Embodiment of Present Disclosure>

FIG. 1-A is a schematic plan view schematically illustrating a semiconductor package according to an embodiment of the present disclosure, and FIG. 1-B is a schematic cross-sectional view taken along line I-I in FIG. 1-A. Note that, in each of the following drawings according to the present embodiment, three-dimensional Cartesian coordinates of a right-handed system in which three directions orthogonal to each other are indicated by X, Y, and Z are also illustrated in order to clearly illustrate the shapes and the arrangement state of the structure, but the position of the origin is not particularly specified.

[Configuration of Semiconductor Ceramic Package]

In a semiconductor package 1 according to the present embodiment, a package main body portion 11 has, for example, a laminated structure formed by laminating a plurality of thin ceramic sheets constituted by a ceramic material such as alumina having high insulation properties and a small thermal expansion coefficient. In this package main body portion 11, a semiconductor chip 2 and an inner lead portion 3 are formed as a substantial configuration.

Note that the package main body 11 of the present embodiment is formed by laminating a large number of ceramic sheet materials containing alumina having high electrical insulation properties as a main raw material, but is not particularly limited to this ceramic sheet material. In addition, the forming material is not particularly limited to a material containing the alumina as a main raw material, and aluminum nitride or other materials having high thermal conductivity can be used.

In the present embodiment, the package main body portion 11 has a step shape having a substantially three-step cross-sectional structure from the central portion toward the periphery. The package main body portion 11 includes a substantially rectangular or square bed portion 12 provided at a central portion for mounting the semiconductor chip 2, a first step portion 13 provided one step higher in a step shape so as to surround the periphery of the outer edge portion of the bed portion 12 for installing the inner lead portion 3, and a second step portion 14 provided one step higher in a step shape outside the first step portion 13 so as to further surround the first step portion 12.

In addition, when wiring connection between the semiconductor chip 2 and the outside is completed, specifically, for example, wiring connection between the semiconductor chip 2 and the inner lead 3 and wiring connection between the inner lead 3 and an outer lead (not illustrated) or the like is completed, and then the package main body portion 11 is molded with an appropriate resin to perform resin sealing. Note that, instead of the resin sealing, the package main body portion 11 may be sealed from above with a lid portion (not illustrated) prepared in advance constituted by an appropriate metal.

The bed portion 12 has a substantially rectangular shape or a square shape whose vertical and horizontal sizes are slightly larger than the outer shape of the mounted semiconductor chip 2, and is fixed in a state where a part (lower portion side) of the semiconductor chip 2 is embedded.

The first step portion 13 is formed in a square shape in plan view, and as described above, the inner lead portion 3 including a plurality of inner leads 31 is disposed in the first step portion 13.

Similarly to the first step portion 13, the second step portion 14 has a square shape, and is provided one step higher around the first step portion 13 so as to surround the first step portion 13. Therefore, for example, in a case where the wiring connection between the outer lead portion (not illustrated) and the inner lead portion 3 is performed, a gold wire (Au wire) or the like can be wired by a wire bonder or the like in a state of going over the second step portion 14.

The semiconductor chip 2 of the present embodiment is mounted and fixed in a state where the lower half is embedded in the bed portion 12. On the upper surface of the semiconductor chip 2, as illustrated in FIG. 2, a large number of (72 in the present embodiment) bonding pads (hereinafter, may be referred to as a “pad electrode”) 21 having a rectangular shape or a square shape are formed in a high-density state in which the bonding pads are arranged in a matrix in the XY-two-dimensional direction.

The inner lead portion 3 can be electrically connected to a terminal of the semiconductor chip 2, that is, the pad electrode 21 by a wire bondender using, for example, a gold wire (Au wire) or the like. In particular, in the present disclosure, in order to enable wiring connection even in the semiconductor chip 2 having a large number of pad electrodes 21, four inner leads 31 each having an I-shape, in other words, a ribbon shape (hereinafter, this may be referred to as a “ribbon R”) are provided on all sides along each side of an upper surface 13A portion having the square shape in plan view of the first step portion 13.

[Specific Configuration of Inner Lead Portion]

(1-1. First Configuration Example)

As illustrated in FIG. 2, the inner lead portion 3 (in the present configuration example, referred to as an “inner lead portion 3A”) of the semiconductor package 1 (in the present configuration example, referred to as a “semiconductor package 1A”) of the first configuration example according to the present embodiment is formed in a square-shaped pattern (hereinafter, may be referred to as a “frame pattern”) similar to the upper surface 13A, in which the outer peripheral length of each side is L′ and the width of each side is w, in the upper surface 13A of the square-shaped first step portion 13 having a constant length L and a constant width W.

That is, the inner lead portion 3A of the present configuration example is formed and disposed in this frame pattern by a conductive metal foil (gold foil in the present embodiment) or the like.

Note that, as a pattern shape of the inner lead portion 3A formed on the upper surface 13A, formation patterns of various modes can be used as described later. For example, in the inner lead portion 3A of the present configuration example, each inner lead 31 can be formed in a shape of a ribbon R having a length s and a width w along each side (length L) of the upper surface 13A as indicated by cross hatching in FIG. 2. That is, each inner lead 31 can be configured as a long rectangular (ribbon) shaped wiring connection conductor (hereinafter, this may be referred to as “ribbon R”).

In other words, as illustrated in FIGS. 1-A and 5-A, for example, the inner lead portion 3A of the present configuration example can be configured by four ribbons R having the same shape, and can be sequentially arranged side by side in a cyclic manner by deflecting the direction by 90 degrees clockwise from each other on the upper surface 13A (see FIGS. 1-B) of the first step portion 13.

As illustrated in FIG. 2, the ribbons R have a complementary arrangement configuration in which a portion of the tip end side of the ribbon R next to each other enters by the width w in the shaded region (hereinafter, this may be referred to as an “insertion portion H”). Therefore, each of the ribbons R has a length s (where s<L′) and a width w.

The length s of each of the ribbons R is obtained by subtracting the length w of the insertion portion H on the tip end portion side of the next ribbon R and the insulation area NC (=d). Specifically, in FIG. 2, each ribbon R has a length s (=L′−(w+d)) obtained by subtracting a sum of a length w of the insertion portion H entering on the tip end side of the adjacent ribbon R and a length d of the insulation area NC for achieving insulation with the adjacent ribbon R from a length L′ of each side of the frame pattern.

Note that, as described above, the insulation area NC separates the adjacent ribbons R by a predetermined length (hereinafter, this may be referred to as a “cut portion D”: see FIG. 4) to impart independence to the ribbons R. That is, by separating the ribbons R from the adjacent ribbons R, the upper surface 13A of the first step portion 13 constituted by a ceramic material such as alumina having high insulation properties and a small thermal expansion coefficient is interposed between the ribbons R, so that sufficient insulation can be secured.

Further, in the present configuration example, as an arrangement mode at the corner portion between the inner lead portions 3A, for example, an α portion in FIG. 5-A can be arranged as illustrated in FIG. 6-A.

In the present embodiment, the inner lead portion 3A provided on each side of the upper surface 13A is formed by arranging seven inner leads 31 in parallel to each other as illustrated in FIGS. 1-A and 1-B. The inner lead 31 can maintain a stable connection state by using the same metal as the wire material (hereinafter, this is referred to as a “bonding wire”) to be bonded. Therefore, in the present embodiment, a gold wire (Au wire) is used for the bonding wire, and the same gold (Au) is also used for the inner lead 31 and formed on the upper surface 13A in a predetermined pattern shape.

In particular, in the present embodiment, the package main body portion 11 is formed by laminating a large number of thin ceramic sheets constituted by a ceramic material such as alumina having high insulation properties and a small thermal expansion coefficient, for example. Therefore, in the inner lead 31 according to the present embodiment, when the upper surface 13A of the first step portion 13 of the package main body portion 11 is formed, in at least the uppermost ceramic sheet of the first step portion 13 (further, depending on the thickness of the ceramic sheet, in a plurality of ceramic sheets below the ceramic sheet), a metal foil having good conductivity, for example, gold (Au) in the present configuration example, is formed with a predetermined wiring pattern determined in advance through a predetermined work process.

Further, as illustrated in FIG. 3, the inner lead 31 of the present disclosure has a configuration in which island portions 310 bulging laterally with respect to the wiring direction are provided at a plurality of places at a required pitch interval. That is, in the inner lead 31, when the inner lead 31 and the pad electrode 21 on the semiconductor chip 2 side are connected, a large number of island portions 310 are formed in order to freely select a connection portion of the bonding wire, which is the lead-out wiring, in the inner lead 31.

These island portions 310 have a circular shape in the case of the present embodiment, but are not particularly limited to this shape, and may have any form of an elliptical shape, a rhombus shape, and a rectangular shape, or the like, for example. In addition, in order to reduce an installation space by narrowing an arrangement interval between the inner leads 31, the island portions 310 are formed in an arrangement state in which positions are shifted by a half pitch from each other so that the island portions 310 provided in the adjacent inner leads 31 do not collide with each other.

Note that the semiconductor package of the present disclosure is not particularly limited to a combination of a material such as gold wire for a bonding wire and gold foil for a pattern wiring as in this embodiment, and aluminum (Al), copper (Cu), or the like can be used for a bonding wire and a pattern wiring. For example, gold (Au) may be used for the bonding wire and aluminum (Al) may be used for the pattern wiring. In this case, when thermocompression bonding is performed with a wire bonder, an alloy layer is formed by a thermal reaction (gold aluminum reaction), so that firm connection can be performed.

Therefore, according to the present configuration example, for example, in FIG. 3, while the number of pad electrodes 21 of the semiconductor chip 2 is 72 (=9 rows×8 columns), the number of inner leads 31 is 28 (=7×4 locations) assuming seven at each of four locations of the upper, lower, left, and right. Therefore, it is necessary to connect approximately three bonding wires on average per one inner lead 31, the bonding wires being drawn one by one from each pad electrode 21. Therefore, in each inner lead 31, it is necessary to divide one inner lead 31 into three on average.

Therefore, such a case can be handled by the following method. This will be described with reference to FIG. 4.

For example, in FIG. 4, a tip end portion of a bonding wire W1 whose base end portion is connected to and wired with a pad electrode 21A of the semiconductor chip 3 is welded to the island 310A. Similarly, a tip end portion of a bonding wire W2 whose base end portion is connected to and wired with a pad electrode 21B of the semiconductor chip 3 is welded to the island 310B.

In this case, since the two pad electrodes 21A and 21B of the semiconductor chip 3 are electrically connected to the same inner lead 31, a connection failure occurs as it is. Therefore, in a case where the inner leads 31, which are the connection destinations on the tip end sides of two bonding wires W, are the same, it is necessary to discontinue the connection states of the two bonding wires W. Therefore, for example, a dedicated fusing means is provided in advance in a semiconductor manufacturing apparatus or the like, and as illustrated in FIG. 4, the cut portion D can be formed by fusing between the islands 310A and 310B of the inner lead 31. As a result, even in a case where a large number of bonding wires are connected to the same inner lead, it is possible to eliminate the imperfection of the connection state by partially forming the cut portion D.

Moreover, as in the present embodiment, since a large number of islands 310 are formed in a single inner lead 31, even in a case where the connection between the tip end side of the bonding wire W and an island 310 fails, it is possible to reconnect to another island 310.

As described above, as illustrated in FIG. 5-A, the inner lead portion 3A of the present embodiment has a structure having a square shape in which four ribbons R are complementarily and sequentially arranged side by side in a cyclic manner along the periphery of four sides on the outer edge side of the bed portion 12 when viewed as an entire shape. In addition, the inner lead 31 constituting the inner lead portion 3A can also be said to have an arrangement structure in which the inner lead is wound in a plurality of layers concentrically (this may be referred to as a “spiral shape”) along the periphery of the four sides on the outer edge side of the bed portion 12 when viewed as an entire shape.

Therefore, according to the semiconductor package of the present configuration example, when focusing on an arbitrary pad electrode 21 of the semiconductor chip 2, for example, as illustrated in FIG. 2, regarding a pad electrode 21C disposed in the substantially central portion of the semiconductor chip 2, the bonding wire drawn out from the pad electrode and wired and connected to the inner lead 31 can be easily wired and connected to any of the four ribbons R of the upper, lower, left, and right of the inner lead portion 3A.

On the other hand, for a pad electrode 21D provided on the upper side of the semiconductor chip 2 in FIG. 2, for example, avoiding the pad electrode in the substantially central portion of the semiconductor chip 2, the nearest ribbon R is on the left side or on the upper side as illustrated in FIG. 3, for example. Therefore, in this case, wiring connection with an arbitrary island portion 310 of a left inner lead 31L or an upper inner lead 31U is straightforward routing. In addition to this, wiring connection with the inner leads 31 of the ribbons R on the upper side, the right side, and the lower side is not impossible, and the inner leads 31 to be wired can be selected for those in all directions of approximately 360 degrees.

Note that, in the present embodiment, each inner lead 31 has a pattern structure in which the entire length is formed along each side on the outer edge side of the bed portion 12 in each winding to surround the entire four sides, but is not particularly limited to this pattern mode. For example, the pattern structure may be formed over three sides on the outer edge side of the bed portion 12, or two sets may be formed over two sides on the outer edge side of the bed portion 12. These various aspects will be described later.

(1-2. Second Configuration Example)

Next, an inner lead portion 3B of a second aspect (hereinafter referred to as a “second configuration example”) according to the present disclosure will be described with reference to FIG. 5-B. Note that, in the present configuration example, the same parts as those in the first configuration example are denoted by the same reference numerals, and redundant description is avoided.

In a semiconductor package 1B of the present configuration example, as illustrated in the drawing, two I-shaped inner lead portions 3B are arranged side by side at predetermined intervals along each side of the bed portion 12, and a total of eight inner lead portions 3B are formed.

Further, in the present configuration example, as an arrangement mode at the corner portions between the inner lead portions 3B, for example, a R portion in FIG. 5-B can be arranged as illustrated in FIG. 6-B.

[Effects of Second Configuration Example]

Therefore, according to the present configuration, in a case where the bonding wire is drawn out from the pad electrode of the semiconductor chip 2 to the inner lead portion 3B, the number of the closest inner leads as connection targets is smaller than that of the first configuration example, but the total number of the inner leads is doubled, which is suitable for application to a semiconductor chip having a terminal with a higher density.

(1-3. Third Configuration Example)

Next, an inner lead portion 3C of a third aspect (hereinafter, referred to as a “third configuration example”) according to the present disclosure will be described with reference to FIG. 5-C. Note that, in the present configuration example, the same parts as those of the first and second configuration examples are denoted by the same reference numerals, and redundant description is avoided.

A semiconductor package 1C of the present configuration example is different from the first and second configuration examples in that the inner lead portion 3C is formed in a substantially L shape and is constituted by two components.

Further, in the present configuration example, as an arrangement mode at the corner portion between the inner lead portions 3C, for example, a y portion in FIG. 5-C can be arranged as illustrated in FIG. 6-C.

[Effects of Third Configuration Example]

Therefore, according to the present configuration, in a case where the bonding wire is drawn out from the pad electrode of the semiconductor chip 2 to the inner lead portion 3B, the number of the closest inner leads as connection targets is 14 (=7×2 locations). Therefore, the total number of inner leads is smaller than that in the first and second configuration examples, but the closest inner lead as connection targets is expanded to the range of 180 degrees, and accordingly, the drawing direction of the inner lead as connection targets is twice as large as that in the first configuration example and 4 times as large as that in the second configuration example. As a result, the layout of the bonding wire is greatly expanded.

(1-4. Fourth Configuration Example)

Next, an inner lead portion 3D of a fourth aspect (hereinafter, referred to as a “fourth configuration example”) according to the present disclosure will be described with reference to FIG. 5-D. Note that, also in the present configuration example, the same parts as those in the previous configuration examples are denoted by the same reference numerals, and redundant description is avoided.

The semiconductor package 1D of the present configuration example is different from the first to third configuration examples in that the inner lead portion 3D is formed in a substantially U shape and is constituted by a single component.

[Effects of Fourth Configuration Example]

Therefore, according to the present configuration, in a case where the bonding wire is drawn out from the pad electrode of the semiconductor chip 2 to the inner lead portion 3D, the number of inner leads as connection targets is seven. Therefore, the total number of inner leads is smaller than that in the first to third configuration examples. However, the inner lead as connection targets is enlarged over the entire circumference of approximately 360 degrees, and accordingly, the drawing direction to the inner lead is twice as large as that in the first configuration example, 4 times as large as that in the second configuration example, and twice as large as that in the third configuration example. As a result, the layout pattern of the bonding wire is greatly enlarged.

<3. Configuration that can be Taken by Present Disclosure>

It is to be noted that the technology of the present disclosure may have the following configurations.

(1) A semiconductor package including: a package main body portion; a bed portion which is provided on a center side of the package main body portion and on which a semiconductor chip is mounted; and an inner lead portion formed in a plurality of turns to surround a periphery of an outer edge side of the bed portion, the inner lead portion including a plurality of inner leads for establishing connection with the semiconductor chip.

(2) The semiconductor package according to (1),

- in which a plurality of the inner leads is disposed in a spiral shape to surround a periphery of the semiconductor chip.

(3) The semiconductor package according to (1) or (2), in which each of the inner leads has an island portion bulging laterally with respect to a wiring direction at a plurality of locations.

(4) The semiconductor package according to any one of (1) to (3), in which each of the inner leads is arranged side by side in a rectangular shape in a plurality of turns around four sides of outer edge sides of the bed portion having a substantially rectangular shape, and each of the inner leads has a configuration in which an entire length in each winding is: ⋅formed over an entire of the four outer edge sides of the bed portion; ⋅formed over three sides of the outer edge sides of the bed portion; ⋅formed over two sides of the outer edge sides of the bed portion; or ⋅formed in units of each side of the outer edge sides of the bed portion.

(5) The semiconductor package according to (3), in which the island portion has any one of a circular shape, an elliptical shape, a rhombus shape, and a rectangular shape.

(6) The semiconductor package according to any one of (1) to (5), in which the package main body portion is constituted by ceramic.

REFERENCE SIGNS LIST

- 1, 1A, 1B, 1C, 1D Semiconductor package
- 11 Package main body portion
- 12 Bed portion
- 13 First step portion
- 13A Upper surface
- 14 Second step portion
- 2 Semiconductor chip
- 21, 21A, 21B, 21C, 21D Bonding pad (pad electrode)
- 3, 3A, 3B, 3C, 3D Inner lead portion
- 31 Inner lead (wiring connection conductor: ribbon)
- 31L Left inner lead
- 31U Upper inner lead
- 310, 310A, 310B Island portion
- D Cut portion
- d Length of insulation area
- H Insertion portion of next inner lead
- L Length of upper surface of first step portion
- L′ Side length of each inner lead portion (including insertion
- portion of next inner lead)
- NC Insulation area
- R Ribbon (wiring connection conductor)
- s Length of inner lead
- W, W1, W2 Bonding wire
- w Inner lead width

SEMICONDUCTOR PACKAGE

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