Claims
- 1. A semiconductor plasma processing apparatus for processing a semiconductor wafer, comprising:a sensor for monitoring at least one processing state of said semiconductor plasma processing apparatus; first and second processing state monitoring units coupled to said sensor; and a selector unit for selecting one of said first and second processing state monitoring units; wherein said first processing state monitoring unit includes: processing result input means for inputting externally measured values for processing results of a semiconductor wafer processed by said semiconductor processing apparatus in a pre-trial; a model equation generation unit which generates a model equation for predicting a processing result using sensed data acquired by said sensor as an explanatory variable, based on said sensed data and said externally measured values; a processing result prediction unit for predicting a processing result based on said model equation and said sensed data; and a process recipe control unit for comparing said predicted processing result with a pre-set value to control a processing condition of said semiconductor plasma processing apparatus such that a deviation between said predicted processing result and said pre-set value is corrected; and wherein said second processing state monitoring includes: a principal component extraction unit for extracting a principal component based on sensed data acquired by said sensor; and a fault detection unit for detecting a fault in processing based on variations in the principal component extracted by said extraction unit.
- 2. A semiconductor plasma processing apparatus according to claim 1, wherein said principal component extraction unit extracts the principal component from a variety of types of sensed data acquired by said sensor.
- 3. A semiconductor plasma processing apparatus according to claim 1, wherein said selection unit selects said second processing state monitoring unit in response to a determination of no model equation preserved for the semiconductor wafer which is being processed.
CROSS REFERENCE TO RELATED APPLICATION
This is a continuation of U.S. application Ser. No. 10/196,208, filed Jul. 17, 2002, now U.S. Pat. No. 6,706,543, which is a divisional of U.S. application Ser. No. 09/946,732, filed Sep. 6, 2001, now U.S. Pat. No. 6,616,759, the subject matter of which is incorporated by reference herein.
US Referenced Citations (8)
Foreign Referenced Citations (2)
Number |
Date |
Country |
10-125660 |
May 1998 |
JP |
11-87323 |
Mar 1999 |
JP |
Continuations (1)
|
Number |
Date |
Country |
Parent |
10/196208 |
Jul 2002 |
US |
Child |
10/438842 |
|
US |