Patent Application
20250183134
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor power module, a motor controller, and a vehicle.
Semiconductor power modules are widely used in industry. The semiconductor power module is usually used to convert an alternating current into a direct current, or convert a direct current into an alternating current. The semiconductor power module has advantages such as high integration and a small volume. However, in an inversion process, a voltage generated by a stray inductance of a loop during switching of a semiconductor chip is excessively large, and electromagnetic interference is generated due to damped oscillation, which increases a switching loss. In addition, if a high current is to be output, multiple chips need to be connected in parallel, and thus a region occupied by the chips is large, and an inductance is also increased accordingly.
The present disclosure resolves at least one of the technical problems in the prior art. Therefore, the present disclosure is to provide a semiconductor power module. The semiconductor power module has advantages such as a small stray inductance and a good heat dissipation effect.
The present disclosure further provides a motor controller having the foregoing semiconductor power module.
The present disclosure further provides a vehicle having the foregoing motor controller.
A first aspect of an embodiment according to the present disclosure provides a semiconductor power module, including: a substrate including a first direction and a second direction orthogonal to each other; a first conductive region including a first transverse section and a second transverse section; a second conductive region, the second conductive region and the first conductive region spaced apart on the substrate; the second conductive region including a third transverse section and a fourth transverse section; and the first transverse section, the third transverse section, the second transverse section, and the fourth transverse section disposed in the first direction, where the first conductive region and the second conductive region are configured to transmit DC signals; at least one first power chip connected to the first transverse section and the third transverse section; and at least one second power chip connected to the second transverse section and the fourth transverse section.
According to some embodiments of the present disclosure, the first conductive region further includes a first vertical section, the first transverse section and the second transverse section both extend in the second direction, the first vertical section extends in the first direction, and two ends of the first vertical section are respectively connected to the first transverse section and the second transverse section. The second conductive region further includes a second vertical section, the third transverse section and the fourth transverse section both extend in the second direction, the second vertical section extends in the first direction, and two ends of the second vertical section are respectively connected to the third transverse section and the fourth transverse section. The first vertical section and the second vertical section are respectively arranged/disposed adjacent to two opposite sides of the substrate in the second direction.
According to some embodiments of the present disclosure, a first end of the first vertical section is flush with the second transverse section, a back side of the first transverse section, and a second end of the first vertical section is flush with the first transverse section, a back side of the second transverse section; and a first end of the second vertical section is flush with the fourth transverse section, a back side of the third transverse section, and a second end of the second vertical section is flush with the third transverse section, a back side of the fourth transverse section.
According to some embodiments of the present disclosure, a side of the first vertical section that faces away from the second vertical section is flush with an end of the fourth transverse section away from the second vertical section; and a side of the second vertical section that faces away from the first vertical section is flush with a side of the first transverse section away from the first vertical section.
According to some embodiments of the present disclosure, the first power chip is mounted on the third transverse section, and the first power chip is connected to the first transverse section through a first connection member.
According to some embodiments of the present disclosure, the second power chip is mounted on the fourth transverse section, and the second power chip is connected to the second transverse section through a second connection member.
According to some embodiments of the present disclosure, the semiconductor power module includes: a third conductive region. The third conductive region is arranged on the substrate and spaced apart from the first conductive region and the second conductive region, and the third conductive region is disposed around the first conductive region and the second conductive region in a closed loop shape.
According to some embodiments of the present disclosure, the third conductive region includes a third vertical section, a fourth vertical section, a fifth transverse section, and a sixth transverse section. The third vertical section and the fourth vertical section extend in the first direction and are spaced apart in the second direction; the fifth transverse section and the sixth transverse section extend in the second direction and are spaced apart in the first direction; the third vertical section, the fifth transverse section, the fourth vertical section, and the sixth transverse section are connected end to end; and the first conductive region and the second conductive region are located between the third vertical section and the fourth vertical section in the second direction; the fifth transverse section is located on the side of the fourth transverse section that faces away from the third transverse section in the first direction, where the third conductive region is configured to transmit DC signals. The semiconductor power device includes: at least one third power chip and at least one fourth power chip. The third power chip is disposed on the fifth transverse section, the third power chip is connected to the fourth transverse section, the fourth power chip is disposed on the fifth transverse section, and the fourth power chip is connected to the fourth transverse section.
According to some embodiments of the present disclosure, multiple third power chips are included, the multiple third power chips are spaced apart in the second direction, and the multiple third power chips are disposed in a row in the second direction. Multiple fourth power chips are included, the multiple fourth power chips are spaced apart in the second direction, and the multiple fourth power chips are disposed in a row in the second direction. The row in which the third power chips are located and the row in which the fourth power chips are located are spaced apart in the first direction. A sum of a quantity of first power chips and a quantity of second power chips and a sum of a quantity of the third power chips and a quantity of the fourth power chips are the same.
According to some embodiments of the present disclosure, the multiple third power chips and the multiple fourth power chips are alternately disposed in the second direction.
According to some embodiments of the present disclosure, the semiconductor power device includes: a fourth conductive region. The fourth conductive region is disposed on the substrate and is spaced apart from the first conductive region, the second conductive region, and the third conductive region. The fourth conductive region extends in the second direction and is located on a side of the fifth transverse section that faces away from the fourth transverse section, and the third power chip and the fourth power chip are both connected to the fourth conductive region. The fourth conductive region is configured to transmit AC signals.
According to some embodiments of the present disclosure, the third power chip is connected to the fourth transverse section through a third connection member, and the third power chip is connected to the fourth conductive region through a fourth connection member.
According to some embodiments of the present disclosure, the third connection member and the fourth connection member are formed as an integrated member extending in the first direction.
According to some embodiments of the present disclosure, the fourth connection member and the fourth power chip are spaced apart in the second direction.
According to some embodiments of the present disclosure, the fourth power chip is connected to the fourth transverse section through a fifth connection member; and the fourth power chip is connected to the fourth conductive region through a sixth connection member.
According to some embodiments of the present disclosure, the fifth connection member and the sixth connection member are constructed as an integrated member extending in the first direction.
According to some embodiments of the present disclosure, the fifth connection member and the third power chip are spaced apart in the second direction.
According to some embodiments of the present disclosure, the semiconductor power device includes: a first DC transmission terminal, the first DC transmission terminal being connected to the first transverse section and extending beyond an edge of the substrate; a second DC transmission terminal, the second DC transmission terminal being connected to an end of the third vertical section away from the fifth transverse section and extending beyond the edge of the substrate; a third DC transmission terminal, the third DC transmission terminal being connected to an end of the fourth vertical section away from the fifth transverse section and extending beyond the edge of the substrate; and an AC transmission terminal, the AC transmission terminal being connected to the fourth conductive region and extending beyond the edge of the substrate.
According to some embodiments of the present disclosure, a low-voltage connection part is arranged on the side of the first transverse section that faces away from the second transverse section, a length of the low-voltage connection part is less than a length of the first transverse section and greater than a width of the first DC transmission terminal, and the first DC transmission terminal is connected to the low-voltage connection part.
According to some embodiments of the present disclosure, a first high-voltage connection part is arranged on the end of the third vertical section away from the fifth transverse section, a size of the first high-voltage connection part in the second direction is greater than a width of the third vertical section and greater than a width of the second DC transmission terminal, and the second DC transmission terminal is connected to the first high-voltage connection part. A second high-voltage connection part is arranged on the end of the fourth vertical section away from the fifth transverse section, a size of the second high-voltage connection part in the second direction is greater than a width of the fourth vertical section and greater than a width of the third DC transmission terminal, and the third DC transmission terminal is connected to the second high-voltage connection part.
According to some embodiments of the present disclosure, the substrate includes: an insulation layer; a circuit layer, the circuit layer being connected to a side of the insulation layer in a thickness direction, and the first conductive region and the second conductive region being formed on the circuit layer; and a heat dissipation layer, the heat dissipation layer being connected to another side of the insulation layer in the thickness direction.
According to some embodiments of the present disclosure, the semiconductor power device includes: an insulation cover. The insulation cover is mounted on the substrate and covers the first conductive region, the second conductive region, the first power chip, and the second power chip.
According to a second aspect of an embodiment of the present disclosure, a motor controller is provided, including: a heat dissipation bottom plate and a coolant channel, the heat dissipation bottom plate being mounted in the coolant channel; and the semiconductor power device according to the first aspect of the embodiment of the present disclosure, the semiconductor power device being disposed on the heat dissipation bottom plate.
According to the second aspect of the embodiment of the present disclosure, by using the semiconductor power device according to the first aspect of the embodiment of the present disclosure, the motor controller has advantages such as a small stray inductance and a good heat dissipation effect.
According to some embodiments of the present disclosure, multiple semiconductor power devices are disposed on the heat dissipation bottom plate in the second direction.
According to a third aspect of an embodiment of the present disclosure, a vehicle is provided, including: a motor; and the motor controller according to the second aspect of the embodiment of the present disclosure, the motor controller being connected to the motor.
According to the third aspect of the embodiment of the present disclosure, by using the motor controller according to the second aspect of the embodiment of the present disclosure, the vehicle has advantages such as a small stray inductance and a good heat dissipation effect.
Additional aspects and advantages of the disclosure will be given in the following descriptions, some of which will become apparent from the following descriptions or may be learned from practices of the disclosure.
The foregoing and/or additional aspects and advantages of the disclosure will become apparent and comprehensible in the description of the embodiments made with reference to the following accompanying drawings.
The embodiments described with reference to accompanying drawings are examples, and the embodiments of the present disclosure are described in detail below.
In the descriptions of the present disclosure, it should be understood that orientation or position relationships indicated by the terms such as “center”, “longitudinal”, “transverse”, “length”, “width”, “thickness”, “on”, “below”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial direction”, “radial direction”, and “circumferential direction” are based on orientation or position relationships shown in the accompanying drawings, and are used only for ease and brevity of illustration and description, rather than indicating or implying that the mentioned apparatus or component needs to have a particular orientation or needs to be constructed and operated in a particular orientation.
In the descriptions of the disclosure, “a plurality of” means two or more.
A semiconductor power module 1 according to the embodiments of the disclosure is described below with reference to the accompanying drawings.
As shown in
The substrate 100 includes a first direction and a second direction orthogonal to each other. The substrate 100 includes a first conductive region 110 and a second conductive region 120 that are spaced apart on the substrate 100. The first conductive region 110 includes a first transverse section 111 and a second transverse section 112, and the second conductive region 120 includes a third transverse section 121 and a fourth transverse section 122. The first transverse section 111, the third transverse section 121, the second transverse section 112, and the fourth transverse section 122 are sequentially arranged/disposed in the first direction. The first conductive region 110 and the second conductive region 120 are configured to transmit DC signals. The first power chip 200 is connected to the first transverse section 111 and the third transverse section 121, and the second power chip 300 is connected to the second transverse section 112 and the fourth transverse section 122.
In other words, if the first direction is a length direction of the substrate 100, the second direction is a width direction of the substrate 100. In an embodiment, if the first direction is the width direction of the substrate 100, the second direction is the length direction of the substrate 100. This may be configured based on an actual situation, such as a shape of the substrate 100, and is not limited.
For example, the semiconductor power module 1 may be a silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET), or may be a device that cooperates with an IGBT (Insulated Gate Bipolar Transistor) and an FRD (Fast Recovery Diode).
During actual applications, the semiconductor power module 1 needs to be packaged, for example, in a plastic sealing manner, to be specific, a process in which a semi-finished product of the semiconductor power module 1 is injected and molded through plastic sealing. In other words, all structures in the semiconductor power module 1 are mounted in a frame and plastic sealed, to form a plastic-sealed body module. In an embodiment, a potting sealing manner may be used, to be specific, a process in which a semi-finished product of the semiconductor power module 1 is potted and molded by using an insulating material such as silica gel. In other words, all structures in the semiconductor power module 1 are mounted in a frame, and the silica gel is filled into the frame, to form a potting-sealed module.
It should be noted that, the semiconductor power module 1 is a half-bridge power module, and may be used in a half-bridge circuit or a three-phase full-bridge circuit. For the plastic sealing manner, one single semiconductor power module 1 forms one plastic-sealed body, e.g., one half-bridge circuit forms one plastic-sealed body. For the potting sealing manner, either one single semiconductor power module 1 may form one potting-sealed body, e.g., one half-bridge circuit forms one potting-sealed body, or three semiconductor power modules 1 may form one potting-sealed body, e.g., the three-phase full-bridge circuit formed by three half-bridge circuits forms one potting-sealed body.
According to the semiconductor power module 1 in this embodiment of the present disclosure, the first conductive region 110 and the second conductive region 120 are arranged on the substrate 100, to avoid a short circuit problem caused by an overlap between the first conductive region 110 and the second conductive region 120. In addition, the first conductive region 110 includes the first transverse section 111 and the second transverse section 112, the second conductive region 120 includes the third transverse section 121 and the fourth transverse section 122, and the first conductive region 110 and the second conductive region 120 are configured to transmit DC signals. The first transverse section 111 and the second transverse section 112 may be connected in series, and the third transverse section 121 and the fourth transverse section 122 may be connected in series.
In addition, the first transverse section 111, the third transverse section 121, the second transverse section 112, and the fourth transverse section 122 are sequentially arranged in the first direction, the first power chip 200 is connected to the first transverse section 111 and the third transverse section 121, and the second power chip 300 is connected to the second transverse section 112 and the fourth transverse section 122.
If the first power chip 200 is mounted on the first transverse section 111, the second power chip 300 is mounted on the second transverse section 112. If the first power chip 200 is mounted on the third transverse section 121, the second power chip 300 is mounted on the fourth transverse section 122. In other words, the first power chip 200 and the second power chip 300 are both mounted on the first conductive region 110 or the second conductive region 120, so that the first power chip 200 and the second power chip 300 form a series connection.
Because the first power chip 200 and the second power chip 300 are necessarily separated by one of the second transverse section 112 and the third transverse section 121, a distance between the first power chip 200 and the second power chip 300 is larger, so that heat accumulation of the first power chip 200 and the second power chip 300 can be avoided, and a heat dissipation effect of the semiconductor power module 1 can be improved.
For example, when the first power chip 200 and the second power chip 300 are respectively arranged on the first transverse section 111 and the second transverse section 112 of the first conductive region 110, while a connection area between the first power chip 200 and the second power chip 300 and the first conductive region 110 is ensured, a size of the first transverse section 111 and a size of the second transverse section 112 in the second direction do not need to be configured to be excessively large, so that a size of the semiconductor power module 1 in the second direction can be reduced.
In the related art, only the first transverse section and the second transverse section that are sequentially arranged in the first direction are provided, both the first power chip and the second power chip need to be mounted on the first transverse section, both the first power chip and the second power chip are connected to the second transverse section, and the first power chip is at a greater distance from the second transverse section than the second power chip. Therefore, a connection structure between the second transverse section and the first power chip needs to be configured to be long, and thus the connection structure between the second transverse section and the first power chip not only generates more heat, but also has a problem of a large stray inductance. However, in the semiconductor power module 1 in this embodiment of the present disclosure, the first power chip 200 is connected to the third transverse section 121, and the second power chip 300 is connected to the fourth transverse section 122. Therefore, a size of a connection structure between the second conductive region 120 and either of the first power chip 200 and the second power chip 300 is small, which not only generates less heat and facilitates heat dissipation, but also reduces a stray inductance and helps reduce a switching loss.
For example, when the first power chip 200 and the second power chip 300 are respectively arranged on the third transverse section 121 and the fourth transverse section 122 of the second conductive region 120, while a connection area between the first power chip 200 and the second power chip 300 and the second conductive region 120 is ensured, a size of the third transverse section 121 and a size of the fourth transverse section 122 in the second direction do not need to be configured to be excessively large, so that a size of the semiconductor power module 1 in the second direction may be reduced.
In addition, in the related art, the first conductive region is provided with only the first transverse section, that is, the first conductive region is not provided with the second transverse section, and both the first power chip and the second power chip need to be connected to the first transverse section. Therefore, a connection structure between the first transverse section and the second power chip needs to be configured to be long, and thus the connection structure between the first transverse section and the second power chip not only generates more heat, but also has a problem of a large stray inductance. However, in the semiconductor power module 1 in this embodiment of the present disclosure, the first power chip 200 is connected to the first transverse section 111, and the second power chip 300 is connected to the second transverse section 112. Therefore, a size of a connection structure between the first conductive region 110 and either of the first power chip 200 and the second power chip 300 is small, which not only generates less heat and facilitates heat dissipation, but also reduces a stray inductance and helps reduce a switching loss.
In summary, it can be learned that the semiconductor power module 1 in this embodiment of the present disclosure has a small stray inductance, a low temperature at a position of the power chip, and a very good heat dissipation effect, which is conducive to applying the semiconductor power module 1 to a circuit with a high switching speed.
In this way, the semiconductor power module 1 according to this embodiment of the present disclosure has advantages such as the small stray inductance and the good heat dissipation effect.
According to some embodiments of the present disclosure, in
In other words, the first conductive region 110 forms a “U”-shaped structure, and the second conductive region 120 forms a “U”-shaped structure. The first conductive region 110 is inserted into the second conductive region 120 from an opening of the second conductive region 120, and the second conductive region 120 is inserted into the first conductive region 110 from an opening of the first conductive region 110.
In this way, the first transverse section 111 and the second transverse section 112 are connected in series through the first vertical section 113, and the third transverse section 121 and the fourth transverse section 122 are connected in series through the second vertical section 123, so that the first power chip 200 and the second power chip 300 can be connected in series, and the first conductive region 110 and the second conductive region 120 occupy less space as a whole.
According to some embodiments of the present disclosure, in
In other words, a sum of sizes of the first vertical section 113 and the fourth transverse section 122 in the first direction is equal to a sum of sizes of the second vertical section 123 and the first transverse section 111 in the first direction. In this way, the first conductive region 110 and the second conductive region 120 occupy less space as a whole in the first direction, and the first power chip 200 and the second power chip 300 are distributed more evenly in the first direction.
According to some embodiments of the present disclosure, in
In other words, a length of the first transverse section 111 may be the same as a length of the fourth transverse section 122, a length of the second transverse section 112 may be the same as a length of the third transverse section 121, a sum of sizes of the second transverse section 112 and the second vertical section 123 in the second direction is substantially equal to the length of the first transverse section 111, and a sum of sizes of the third transverse section 121 and the first vertical section 113 in the second direction is substantially equal to the length of the fourth transverse section 122.
In this way, the first conductive region 110 and the second conductive region 120 occupy less space as a whole in the second direction, thus helping to reduce a volume of the semiconductor power module 1.
According to some embodiments of the present disclosure, in
In this way, the first connection member 210 and the first power chip 200 can implement a connection between the first conductive region 110 and the second conductive region 120. In addition, a length of the first connection member 210 is short, so that a parasitic inductance generated by the first connection member 210 in a circuit can be reduced, thereby reducing a switching loss, and an internal layout is more proper.
According to some embodiments of the present disclosure, in
In this way, the second connection member 310 and the second power chip 300 can implement a connection between the first conductive region 110 and the second conductive region 120. In addition, a length of the second connection member 310 is short, so that a parasitic inductance generated by the second connection member 310 in a circuit can be reduced, thereby reducing a switching loss, and an internal layout is more proper. In addition, the first power chip 200 and the second power chip 300 are more dispersed, so that heat accumulation may be reduced, thereby improving a heat dissipation capability of the semiconductor power module 1.
According to some embodiments of the present disclosure, in
The third conductive region 130 is arranged on the substrate 100 and is spaced apart from the first conductive region 110 and the second conductive region 120, and the third conductive region 130 is constructed in a closed loop shape arranged around the first conductive region 110 and the second conductive region 120.
In an embodiment, the third conductive region 130 includes a third vertical section 131, a fourth vertical section 132, a fifth transverse section 133, and a sixth transverse section 134. The third vertical section 131 and the fourth vertical section 132 extend in the first direction and are spaced apart in the second direction, the fifth transverse section 133 and the sixth transverse section 134 extend in the second direction and are spaced apart in the first direction. The third vertical section 131, the fifth transverse section 133, the fourth vertical section 132, and the sixth transverse section 134 are sequentially connected end to end. The first conductive region 110 and the second conductive region 120 are located between the third vertical section 131 and the fourth vertical section 132 in the second direction. The fifth transverse section 133 is located on a side of the fourth transverse section 122 that faces away from the third transverse section 121 in the first direction, the third conductive region 130 is configured to transmit the DC signals, and the third power chip 400 and the fourth power chip 500 are arranged on the fifth transverse section 133 and are both connected to the fourth transverse section 122.
In other words, the first power chip 200, the second power chip 300, the third power chip 400, and the fourth power chip 500 are respectively arranged in the first conductive region 110, the second conductive region 120, and the third conductive region 130, thereby avoiding a problem of heat increase caused by a compact power chip layout, and improving the heat dissipation capacity of the semiconductor power module 1.
In addition, the third power chip 400 and the fourth power chip 500 form a series connection on the third conductive region 130. Through this configuration, inductances formed inside the semiconductor power module 1 may cancel each other when the semiconductor power module 1 works, so as to effectively reduce a parasitic inductance of the entire module, and to optimize a structural layout inside the semiconductor power module 1, thereby improving integration of the semiconductor power module 1.
In addition, both the third power chip 400 and the fourth power chip 500 are connected to the second conductive region 120, so that the first conductive region 110, the second conductive region 120, and the third conductive region 130 are electrically connected to each other, and the semiconductor power module 1 can implement DC input/output.
According to some embodiments of the present disclosure, in
For example, the third power chips 400 may be in a one-to-one correspondence with the first power chips 200, and the fourth power chips 500 may be in a one-to-one correspondence with the second power chips 300. In addition, a sum of the quantities of the first power chips 200 and the second power chips 300 may be configured based on an output current of the semiconductor power module 1. For example, the sum of the quantities of the first power chips 200 and the second power chips 300 may be 6, 7, or 8. Certainly, the sum of the quantities of the first power chips 200 and the second power chips 300 may be another number, provided that usage requirements of different scenarios of the semiconductor power module 1 are met.
According to some embodiments of the present disclosure, in
According to some embodiments of the present disclosure, in
In this way, the semiconductor power module 1 can implement a function of circuit conversion between a direct current and an alternating current, and the semiconductor power module 1 may be a half-bridge circuit.
According to some embodiments of the present disclosure, in
In other words, the third connection member 410 and the fourth connection member 420 are parallel, the fourth transverse section 122, the fifth transverse section 133, and the fourth conductive region 140 are parallel, and the third connection member 410 and the fourth connection member 420 are respectively perpendicular to the fourth transverse section 122, the fifth transverse section 133, and the fourth conductive region 140.
In this way, lengths of the third connection member 410 and the fourth connection member 420 are smaller, so that a line arrangement can be simplified, and inductances generated by the third connection member 410 and the fourth connection member 420 can be reduced, thereby reducing a switching loss and heat generation, and improving the heat dissipation performance.
According to some embodiments of the present disclosure, in
According to some embodiments of the present disclosure, in
According to some embodiments of the present disclosure, in
In other words, the fifth connection member 510 and the sixth connection member 520 are parallel, the fourth transverse section 122, the fifth transverse section 133, and the fourth conductive region 140 are parallel, and the fifth connection member 510 and the sixth connection member 520 are respectively perpendicular to the fourth transverse section 122, the fifth transverse section 133, and the fourth conductive region 140.
In this way, lengths of the fifth connection member 510 and the sixth connection member 520 are smaller, so that a line arrangement can be simplified, and inductances generated by the fifth connection member 510 and the sixth connection member 520 can be reduced, thereby reducing a switching loss and heat generation, and improving the heat dissipation performance.
According to some embodiments of the present disclosure, in
According to some embodiments of the present disclosure, in
According to some embodiments of the present disclosure, in
The first DC transmission terminal 600 is connected to the first transverse section 111 and extends beyond the edge of the substrate 100, the second DC transmission terminal 700 is connected to an end of the third vertical section 131 away from the fifth transverse section 133 and extends beyond the edge of the substrate 100, the third DC transmission terminal 800 is connected to an end of the fourth vertical section 132 away from the fifth transverse section 133 and extends beyond the edge of the substrate 100, and the AC transmission terminal 900 is connected to the fourth conductive region 140 and extends beyond the edge of the substrate 100.
For example, the first DC transmission terminal 600, the second DC transmission terminal 700, and the third DC transmission terminal 800 are located on one of two opposite sides of the substrate 100, and the AC transmission terminal 900 is located on the other of the two opposite sides of the substrate 100. In this way, a connection between the alternating current and the direct current does not interfere with each other, and electrical connection safety is improved. In addition, a conductive circuit between the second DC transmission terminal 700 and the AC transmission terminal 900 may form a first bridge arm, and a conductive circuit between the third DC transmission terminal 800 and the AC transmission terminal 900 may form a second bridge arm. Inductances formed between a circuit formed by the first bridge arm and a circuit formed by the second bridge arm cancel each other out, thereby reducing a parasitic inductance of the entire semiconductor power module 1, improving a filtering capability of the semiconductor power module 1, and reducing a switching loss.
In
According to some embodiments of the present disclosure, in
By arranging the first high-voltage connection part 710, the third vertical section 131 can be connected to the second DC transmission terminal 700, and in addition, the second DC transmission terminal 700 does not extend beyond the first high-voltage connection part 710 in the second direction, so that a contact area between the second DC transmission terminal 700 and the third vertical section 131 is improved, thereby ensuring reliability of an electrical connection between the second DC transmission terminal 700 and the third vertical section 131.
In addition, the second high-voltage connection part 810 is arranged at an end of the fourth vertical section 132 away from the fifth transverse section 133. A size of the second high-voltage connection part 810 in the second direction is greater than a width of the fourth vertical section 132 and greater than a width of the third DC transmission terminal 800, and the third DC transmission terminal 800 is connected to the second high-voltage connection part 810. A width of the fourth vertical section 132 is less than a width of the third DC transmission terminal 800, so that a size of the semiconductor power module 1 in the second direction is reduced, thereby facilitating miniaturization of the semiconductor power module 1.
By arranging the second high-voltage connection part 810, the fourth vertical section 132 can be connected to the third DC transmission terminal 800, and in addition, the third DC transmission terminal 800 does not extend beyond the second high-voltage connection part 810 in the second direction, so that a contact area between the third DC transmission terminal 800 and the fourth vertical section 132 is improved, thereby ensuring reliability of an electrical connection between the third DC transmission terminal 800 and the fourth vertical section 132.
According to some embodiments of the present disclosure, in
The first high-voltage connection part 710 and the second high-voltage connection part 810 are located on two opposite sides of the low-voltage connection part 610 in the second direction. Through making the length of the low-voltage connection part 610 less than the length of the first transverse section 111, the low-voltage connection part 610 can avoid the first high-voltage connection part 710 and the second high-voltage connection part 810. In addition, while a reliable connection between the low-voltage connection part 610 and the low-voltage connection part 610 is ensured, a size of the semiconductor power module 1 in the second direction is prevented from increasing, thereby facilitating miniaturization of the semiconductor power module 1.
By arranging the low-voltage connection part 610, the first transverse section 111 can be connected to the low-voltage connection part 610, and in addition, the low-voltage connection part 610 does not extend beyond the first transverse section 111 in the second direction, thereby ensuring reliability of an electrical connection between the first DC transmission terminal 600 and the first transverse section 111.
According to some embodiments of this the present disclosure, in
According to some embodiments of the present disclosure, in
The insulation layer 101 may be made of ceramic, for example, made of aluminum oxide (Al2O3), aluminum nitride (AlN), and silicon nitride (Si3N4). In this way, the insulation layer 101 has a good heat conduction effect, a strong insulation capability, and a stable chemical property, which may not only isolate a connection between the conductive layer and the heat dissipation layer 103, but also provide a heat dissipation channel for the semiconductor power module 1.
The circuit layer 102 may be made of a copper material, and the copper is etched into the first conductive region 110, the second conductive region 120, the third conductive region 130, and the fourth conductive region 140. The heat dissipation layer 103 may be made of a copper material, and the first DC transmission terminal 600, the second DC transmission terminal 700, the third DC transmission terminal 800, and the AC transmission terminal 900 may all be made of copper materials. In this way, the circuit layer 102, the heat dissipation layer 103, the first DC transmission terminal 600, the second DC transmission terminal 700, the third DC transmission terminal 800, and the AC transmission terminal 900 all have a good conductivity performance and a heat dissipation performance, and can be effectively connected to an external device.
According to some embodiments of the present disclosure, in
A motor controller 2 according to an embodiment of the present disclosure is described below with reference to the accompanying drawings. In
For example, there are multiple semiconductor power modules 1 and are arranged on the heat dissipation bottom plate 104 in the second direction, and the multiple semiconductor power modules 1 may be arranged in parallel. A bottom of each semiconductor power module 1 is welded to the heat dissipation bottom plate 104. The coolant channel 1200 may be an open-groove water channel, and the heat dissipation bottom plate 104 is mounted on the open groove of the coolant channel 1200, so that a heat dissipation function for the semiconductor power module 1 is implemented. This design is simple, easy to implement, and convenient to operate.
In this embodiment, the semiconductor power module 1 provided based on the foregoing embodiments has a uniform structural layout and a good heat dissipation effect, and the motor controller 2 can be used in various coolant channel applications, such as a series coolant channel or a parallel coolant channel, so that application flexibility of the motor controller 2 is improved, and a stray inductance in a loop during application is reduced.
By using the semiconductor power module 1 according to the foregoing embodiment of the present disclosure, the motor controller 2 according to the embodiment of the present disclosure has advantages such as a small stray inductance and a good heat dissipation effect.
A vehicle 1000 according to an embodiment of the present disclosure is described below with reference to
By using the motor controller 2 according to the embodiment of the present disclosure, the vehicle according to the embodiment of the present disclosure has advantages such as a small stray inductance and a good heat dissipation effect.
Other configurations and operations of the semiconductor power module 1, the motor controller 2, and the vehicle according to the embodiments of the present disclosure are known to a person of ordinary skill in the art and will not be described in detail herein.
In the description of this specification, the description of the reference terms such as “an embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example”, or “some examples” means that the features, structures, materials or characteristics described with reference to the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, schematic descriptions of the foregoing terms are not necessarily directed at a same embodiment or example.
Although the embodiments of the present disclosure have been shown and described, a person of ordinary skill in the art should understand that various changes, modifications, replacements and variations may be made to the embodiments without departing from the principles and spirit of the present disclosure, and the scope of the present disclosure is as defined by the appended claims and their equivalents.
A first direction is a direction indicated by an arrow A, and a second direction is a direction indicated by an arrow B.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211058483.1 | Aug 2022 | CN | national |
This application is a continuation application of International Patent Application No. PCT/CN2023/110386, filed on Jul. 31, 2023, which is based on and claims priority to and benefits of Chinese Patent Application No. 202211058483.1, filed on Aug. 31, 2022. The entire content of all of the above-referenced applications is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2023/110386 | Jul 2023 | WO |
| Child | 19051012 | US |
