BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a flow diagram of a plasma etching process in accordance with one application of the invention.
FIG. 2A, 2B are section views illustrating a porous silicon oxide insulative layer after plasma etching and after metal deposition, respectively.
FIG. 3 illustrates a SAM alkyl chain adhering to the etched surface of the insulated layer of FIG. 2.
FIG. 4 illustrates in more detail the SAM alkyl chain adhering to the etch surface and the exposed pores in the insulative layer.
FIG. 5 illustrates the head of a SAM chain attached to the exposed SiO2 surface.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
FIG. 1 is a flow diagram of a conventional plasma etching process used in fabricating integrated circuits with stacked metal interconnect layers on the surface of the semiconductor substrate and in which the present invention can be employed. For example, in forming a conductive via or trench from one conductive layer to an underlying conductive layer, a photoresist mask is applied to the stack as shown at 10. The mask covers a top surface of the integrated circuit structure with openings defined therein, through which plasma etching can be employed to remove a dielectric layer between the two metal layers at 12. After the dielectric layer has been etched, the photoresist is stripped and byproducts of the plasma processing are removed at 14.
A barrier layer such as silicon carbide is often employed over a metal layer such as copper to prevent copper ion migration and etch stop. The barrier material must be removed by a second plasma etch at 16 in order to expose the underlying copper metal layer.
Steps 12, 14, 16 can be carried out in a plasma chamber without removal of the etched product. Once the etching processes are completed, the etched structure is removed from the plasma chamber and conventionally moved to a metal depositing chamber for sputtering of a metal barrier layer and the conductive layer for filling the via or trench as shown at 18 and 20. However, the etched structure is particularly susceptible to contamination by moisture uptake, especially for porous silicon oxide material with exposed pores and which becomes hydrophilic and promotes moisture uptake when exposed to ambient conditions.
The conventional process is modified as shown in FIG. 1, by dipping the etched structure in a solution of self-assembled monolayer material as shown at 18 and then drying the structure at 20 before the metal barrier deposition at 22. For silicon and silicon oxide material, preferred SAM materials are alkyl chlorosilane (—SiCO3) or hydroxylsilane (—Si(OH)3) in a suitable solvent such as methanol or ethanol.
FIG. 2A is a section view of the etched porous low k silicon oxide material prior to dipping in the SAM solution. Here, a hard mask 30 overlies the porous silicon oxide material 32 which rests on an etched silicon carbide barrier material 34 over a copper metal interconnect layer 36. The exposed surface of the porous silicon oxide layer 32 becomes hydrophilic and promotes moisture uptake when the sample is exposed to the ambient condition. As noted above, this has negative effect on overall circuit capacitance and provides a source of corrosion for the barrier metal. Further, it is known that the barrier metal can diffuse into the open and connected porous structure which also lowers overall circuit capacitance. FIG. 2B illustrates the cross-section after removal of the hard mask 30 and formation of a metal contact in the via. A SAM layer 38 covers silicon oxide 32 and covers or seals pores in material 32. A metal barrier layer 40 such as TiN is first sputtered or deposited on the barrier layer and etched layers 34 and 36 and then the via or trench is filled with copper or other metal 42.
By dipping the etched structure in a SAM solution at 18 in FIG. 1, self-assembled monolayer including a head group, a tail group, and a alkyl chain therebetween attaches to the silicon oxide surface as shown in FIG. 3. The —OH head group combines with the silicon of the porous insulator with the alkyl chain having sufficient length for assembly by van der Waals force to form a self-assembled monolayer. With present porous silicon oxide material, the alkyl chain is preferably 12-18 units in length. By selecting a tail group of —CH3 termination, overall surface property becomes hydrophobic and moisture uptake is prevented. If the chain link is sufficiently short relative to the size of the pores, the monolayer can attach to the silicon atoms within the pores and effectively fill the pores, as shown in the section view of FIG. 4. Alternatively, if the chains are long relative to the size of the pores, the self-assembled monolayer can cover and effectively seal the pore from exposure to the ambient. FIG. 5 is a sectional view illustrating attachments of the SAM material to the silicon oxide with the silicon atoms sharing oxygen atoms with the OH head group of the monolayer.
Use of a self-assembled monolayer has proved effective in preventing moisture uptake of etched silicon and silicon oxide material and in particular, porous silicon oxide dielectrics. The chain length of the monolayer can be readily tailored for use with pores of increasing size, as is expected in the future.
After forming the monolayer, the SAM molecules on a surface can be further treated with thermal energy or UV radiation which promotes dissociation or bond breakage in the molecule structure. With a desired tail group (for example, metal organic functional groups) these further treatments can deliver the desired elements (metal component only) on the sidewall and inside pore surface of the porous low-k dielectric. It is also possible to select tail groups which can be thermally or photo-activated after forming SAM inside the pores. This further ensures pore sealing by activating cross linking or reactions between the tail groups.
Thus, while the invention has been described with reference to specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications and applications may occur to those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Patent Application
20080064214
