Semiconductor storage device and method of fabrication thereof

Abstract

A semiconductor storage device includes: a MOSFET formed on an SOI layer of the transistor forming region; and a MOS capacitor formed on the SOI layer of the capacitor forming region. The MOSFET includes: a gate insulating film formed; a floating gate electrode; a source layer and a drain layer formed; a channel region; a high-concentration diffusion layer, and impurities of a same type as impurities which are diffused in the channel region are diffused at a high concentration in the high-concentration diffusion layer; and a silicide layer covering the high-concentration diffusion layer and the source layer. The MOS capacitor includes a capacitor electrode at the SOI layer. The capacitor electrode of the MOS capacitor is disposed so as to oppose an end portion of the floating gate electrode of the MOSFET, with the gate insulating film therebetween.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred exemplary embodiments of the present invention will be described in detail based on the following figures, wherein:

FIG. 1 is an explanatory drawing showing a top surface of a semiconductor storage device of a first exemplary embodiment;

FIG. 2 is an explanatory drawing showing a cross-section along cross-section line A-A in FIG. 1;

FIG. 3 is an explanatory drawing showing a cross-section along cross-section line B-B in FIG. 1;

FIG. 4 is an explanatory drawing showing a set state of regions on an SOI layer of the first exemplary embodiment;

FIG. 5 is an explanatory drawing showing a method of fabricating the semiconductor storage device of the first exemplary embodiment;

FIG. 6 is an explanatory drawing showing an erasing operation of a storage element of the first exemplary embodiment;

FIG. 7 is an explanatory drawing showing a writing operation of the storage element of the first exemplary embodiment;

FIG. 8 is an explanatory drawing showing a cross-section of a MOS capacitor of a second exemplary embodiment;

FIG. 9 is an explanatory drawing showing a method of fabricating a semiconductor storage device of the second exemplary embodiment; and

FIG. 10 is an explanatory drawing showing the method of fabricating the semiconductor storage device of the second exemplary embodiment.

Claims

1. A semiconductor storage device comprising: a semiconductor substrate formed by a supporting substrate, a buried oxide film formed on the supporting substrate, and an SOI layer formed on the buried oxide film;an element isolating layer insulating and isolating the SOI layer at a transistor forming region and a capacitor forming region which are set at the semiconductor substrate;a MOSFET formed on the SOI layer of the transistor forming region; anda MOS capacitor formed on the SOI layer of the capacitor forming region,wherein the MOSFET includes:a gate insulating film formed on the SOI layer;a floating gate electrode formed on the gate oxide film;a source layer and a drain layer formed at the SOI layer at both sides of the floating gate electrode;a channel region formed between the source layer and the drain layer;a high-concentration diffusion layer which is formed at the source layer in a vicinity of an interface between the source layer and the channel region, and which contacts the channel region, and impurities of a same type as impurities which are diffused in the channel region are diffused at a high concentration in the high-concentration diffusion layer; anda silicide layer covering the high-concentration diffusion layer and the source layer, andthe MOS capacitor includes:a capacitor electrode at the SOI layer, and impurities of a same type as the source layer are diff-used at a high concentration in the capacitor electrode, andthe capacitor electrode of the MOS capacitor is disposed so as to oppose an end portion of the floating gate electrode of the MOSFET, with the gate insulating film therebetween.

2. The semiconductor storage device of claim 1, wherein at the MOS capacitor, a projecting portion, at which is formed an inclined surface which spreads toward the buried oxide film, is provided at a floating gate electrode side end portion of the capacitor electrode, anda distal end of the projecting portion is made to oppose the floating gate electrode, with the gate insulating film therebetween.

3. The semiconductor storage device of claim 1, wherein given that an electrostatic capacity between the floating gate electrode and the channel region which are connected by the source layer of the MOSFET and the silicide layer and the high-concentration diffusion layer is C2, and an electrostatic capacity between the floating gate electrode and the drain layer is C3,an electrostatic capacity C1 between the floating gate electrode and the capacitor electrode of the MOS capacitor is such that C3<C1<C2.

4. The semiconductor storage device of claim 1, wherein the drain layer is set in an open state, the capacitor electrode is grounded, positive voltage is applied to the source layer, and charges are injected in the floating gate electrode.

5. The semiconductor storage device of claim 1, wherein the source layer is set in an open state, negative voltage is applied to the capacitor electrode, positive voltage is applied to the drain layer, and charges are removed from the floating gate electrode.

6. A method of fabricating a semiconductor storage device having a storage element in which a MOS capacitor and a MOSFET, which are formed on a semiconductor substrate at which an SOI layer is layered on a supporting substrate via a buried oxide film, are connected at one floating gate electrode, the method comprising the steps of: setting a transistor forming region and a capacitor forming region at the SOI layer, and forming an element isolating layer between the transistor forming region and the capacitor forming region;forming a gate insulating film on the SOI layer and the element isolating layer;forming, on the gate oxide film, a floating gate electrode which divides the transistor forming region in two and covers a portion of the capacitor forming region;ion-implanting impurities, which are of a same type as impurities which are diffused in a source layer of the MOSFET, at a high concentration on the SOI layer at both sides of the floating gate electrode of the transistor forming region and on the SOI layer of the capacitor forming region, and forming the source layer and a drain layer of the MOSFET and a capacitor electrode of the MOS capacitor;forming, on the SOI layer of the transistor forming region, a resist mask having an opening portion at a region of the source layer which region is adjacent to the floating gate electrode, and ion-implanting impurities, which are a same type as impurities diffused in a channel region of the MOSFET, at a high concentration into the source layer by using the resist mask as a mask, and forming a high-concentration diffusion layer; andremoving the resist mask, and forming a silicide layer which electrically connects the high-concentration diffusion layer and the source layer.

7. The method of fabricating a semiconductor storage device of claim 6, wherein the step of forming the element isolating layer includes the steps of:forming a silicon nitride film on the SOI layer;forming a resist mask which covers the transistor forming region and the capacitor forming region set at the SOI layer, and exposing the SOI layer by etching the silicon nitride film by using the resist mask as a mask; andremoving the resist mask, oxidizing the exposed SOI layer by LOCOS by using the silicon nitride film as a mask, forming an element isolating layer between the transistor forming region and the capacitor forming region, and forming a projecting portion at an end portion of the SOI layer of the capacitor forming region, andthe step of forming the gate oxide film includes the steps of:removing the silicon nitride film and exposing the SOI layer of the capacitor forming region;forming, on the SOI layer and the element isolating layer, a resist mask having an opening portion exposing the element isolating layer which is above the projecting portion formed at the SOI layer and which is at a region adjacent the projecting portion, and etching the element isolating layer and the buried oxide film by using the resist mask as a mask, and forming a capacitor trench which has a bottom surface within the buried oxide film and which exposes the projecting portion; andremoving the resist mask, and forming a gate insulating film on the SOI layer and the element isolating layer and at an inner surface of the capacitor trench.

8. The method of fabricating a semiconductor storage device of claim 6, wherein the step of forming the element isolating layer includes the steps of:forming a silicon nitride film on the SOI layer;forming a resist mask which covers the transistor forming region and the capacitor forming region set at the SOI layer, and, by anisotropic etching using the resist mask as a mask, etching the silicon nitride film and the SOI layer so as to expose the buried oxide film, and forming an isolating trench which is a side wall of an inclined surface, and forming a projecting portion at an end portion of the SOI layer;removing the resist mask, and depositing silicon oxide on the silicon nitride film and in the isolating trench including the projecting portion; andpolishing the deposited silicon oxide and the silicon nitride film on the SOI layer so as to expose the SOI layer, and forming an element isolating layer between the transistor forming region and the capacitor forming region, andthe step of forming the gate oxide film includes the steps of:forming, on the SOI layer and the element isolating layer, a resist mask having an opening portion exposing the element isolating layer which is above the projecting portion formed at the SOI layer and which is at a region adjacent the projecting portion, and etching the element isolating layer and the buried oxide film by using the resist mask as a mask, and forming a capacitor trench which has a bottom surface within the buried oxide film and which exposes the projecting portion; andremoving the resist mask, and forming a gate insulating film on the SOI layer and the element isolating layer and at an inner surface of the capacitor trench.

9. A semiconductor device comprising: a silicon substrate having a first diffusion layer and a second diffusion layer formed at a silicon substrate region, a third diffusion layer disposed between the first and second diffusion layers, and a fourth diffusion layer provided so as to be insulated and isolated from the first, second, and third diffusion layers;a floating gate electrode overlapping a portion of each of the first and second diffusion layers, and extending from above the third diffusion layer to the fourth diffusion layer;a first control line applying a common first electric potential to the first diffusion layer and the third diffusion layer;a second control line applying a second electric potential to the second diffusion layer; anda third control line applying a third electric potential to the fourth diffusion layer,wherein a surface area over which the floating gate electrode overlaps the fourth diffusion layer is greater than a surface area over which the floating gate electrode overlaps the second diffusion layer, andthe surface area over which the floating gate electrode overlaps the fourth diffusion layer is smaller than a total of surface areas over which the floating gate electrode overlaps the first and third diffusion layers.

10. A semiconductor device comprising: a silicon substrate having a first diffusion layer and a second diffusion layer formed at a silicon substrate region, a third diffusion layer disposed between the first and second diffusion layers, and a fourth diffusion layer provided so as to be insulated and isolated from the first, second, and third diffusion layers;a floating gate electrode overlapping a portion of each of the first and second diffusion layers, and extending from above the third diffusion layer to the fourth diffusion layer;a first control line applying a common first electric potential to the first diffusion layer and the third diffusion layer;a second control line applying a second electric potential to the second diffusion layer; anda third control line applying a third electric potential to the fourth diffusion layer,wherein a capacitance formed between the floating gate electrode and the fourth diffusion layer is greater than a capacitance formed between the floating gate electrode and the second diffusion layer, andthe capacitance formed between the floating gate electrode and the fourth diffusion layer is smaller than capacitances formed by the floating gate electrode and the first and third diffusion layers.

11. The semiconductor device of claim 9, wherein the silicon substrate region is a silicon layer provided on a buried oxide film at an SOI substrate.

12. The semiconductor device of claim 10, wherein the silicon substrate region is a silicon layer provided on a buried oxide film at an SOI substrate.

13. A method of injecting electrons into a floating gate electrode, comprising the step of: in the semiconductor device of claim 9, injecting electrons from the fourth diffusion layer into the floating gate electrode by applying positive electric potential to the first control line and applying ground potential to the third control line.

14. A method of injecting electrons into a floating gate electrode, comprising the step of: in the semiconductor device of claim 10, injecting electrons from the fourth diffusion layer into the floating gate electrode by applying positive electric potential to the first control line and applying ground potential to the third control line.