This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-289357, filed on Nov. 12, 2008, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor storage device such as ferroelectric memory (FeRAM) and a method of manufacturing the same.
2. Description of the Related Art
Storage devices (ferroelectric memory: FeRAM) using ferroelectric capacitors as storage media have been developed and put into practical use (see, for example, Japanese Patent Laid-Open No. 2002-25247). The ferroelectric memory has significant characteristics. For example, stored data will not be lost even after the power is turned off due to its non-volatility, high-speed write and read operations are available because of the capability of rapid inversion of spontaneous polarization when a film thickness of the ferroelectric capacitor is small enough, and so on. In addition, the ferroelectric memory is suitable for large-capacity memory because a memory cell of 1 bit can be configured by one transistor and one ferroelectric capacitor.
With the conventional techniques, it is difficult to deposit a uniform film thickness of not more than 100 nm over the wafer surface due to the morphology of the ferroelectric film (which functions as a ferroelectric capacitor). As such, the ferroelectric film is planarized by Chemical Mechanical Polishing (CMP) and processed to a thickness of not more than 100 nm. The thickness uniformity of the ferroelectric film after the deposition is generally on the order of ±5%.
However, when the CMP process is performed on the ferroelectric film, the thickness uniformity of the ferroelectric film is determined by the thickness uniformity of deposition thereof and thickness uniformity of CMP thereof in the wafer added thereto. Accordingly, after the CMP process, the thickness uniformity of the ferroelectric film within the wafer surface can be up to on the order of ±10%. That is, the CMP degrades the thickness uniformity of the ferroelectric film in the wafer surface. Such degradation in thickness uniformity of the ferroelectric film causes variations in the electric field applied to a ferroelectric material.
In the ferroelectric memory, the polarization of the ferroelectric film is inverted to switch between “1” and “0” as information. Such polarization inversion is caused by an electric field that is equal to or greater than the coercive electric field applied to the ferroelectric capacitor. Consequently, any variations in the electric field applied to the ferroelectric material lead to non-uniform polarization inversion characteristics. That is, this will result in variations in memory characteristics.
One aspect of the present invention provides a semiconductor storage device comprising: a memory cell having a ferroelectric capacitor and a cell transistor connected in parallel, the memory cell comprising: a first conductive layer provided above a substrate; a ferroelectric layer formed on a top surface of the first conductive layer; a second conductive layer formed on a top surface of the ferroelectric layer; and a stopper layer formed in the same layer as the ferroelectric layer, a selection ratio of the stopper layer under CMP being higher than that of the ferroelectric layer under CMP.
In addition, another aspect of the present invention provides a method of manufacturing a semiconductor storage device, the method comprising: depositing a first conductive layer above a substrate; depositing a stopper layer in a certain pattern on a top surface of the first conductive layer; depositing a ferroelectric layer so as to cover the first conductive layer and the stopper layer; planarizing the ferroelectric layer by chemical mechanical polishing so that a top surface of the ferroelectric layer is aligned with a top surface of the stopper layer; and depositing a second conductive layer on the respective top surfaces of the stopper layer and the planarized ferroelectric layer, a selection ratio of the stopper layer under CMP being higher than that of the ferroelectric layer under CMP.
Embodiments of a semiconductor storage device according to the present invention and a method of manufacturing the same will be described below with reference to the accompanying drawings.
(Circuit Configuration of Semiconductor Storage Device 100 in First Embodiment)
Referring first to
Each of the memory cell arrays 1a and 1b includes memory cells MC, each of which includes a ferroelectric capacitor C and a cell transistor Tr. In each of the memory cells MC, the ferroelectric capacitor C and the cell transistor Tr are connected in parallel. In the example illustrated in
The cell blocks MCB0 and MCB1 have one ends N1 connected to the bit lines BL and BBL via block selection transistors BST0 and BST1, and the other ends N2 connected to plate lines PL and BPL. In the respective cell blocks MCB0 and MCB1, the gates of the cell transistors Tr are connected to respective word lines WL0 to WL7.
The bit lines BL and BBL are connected to the sense amplifier circuit 2a (or 2b). In addition, the plate lines PL and BPL are connected to the plate-line drive circuit 3a (or 3b), and the word lines WL0 to WL7 are connected to the sub row decoder circuit 4a (or 4b). Furthermore, the sub row decoder circuits 4a, 4b and the main row decoder circuit 5 are connected to each other by main block selection lines MBS0 and MBS1.
The plate-line drive circuit 3a (or 3b) has a function for selectively driving the plate lines PL and BPL. The sub row decoder circuit 4a (or 4b) has a function for selectively driving the word lines WL0 to WL7. The main row decoder circuit 5 has a function for selectively driving the sub row decoder circuits 4a, 4b using control signals via the main block selection lines MES0 and MBS1.
(Operation of Semiconductor Storage Device 100 in First Embodiment)
Referring now to
As illustrated in
In this case, in the memory cells MC (FeRAM), either a memory cell storing data “1” or a memory cell storing data “0” should necessarily experience inversion of spontaneous polarization when one word line WL is set to “L” for reading and voltage is applied to the ferroelectric capacitors. Accordingly, a rewrite operation is required after the read operation for inverting again the inverted spontaneous polarization based on the read data. As illustrated in FIG. 2B, for example, spontaneous polarization Pr1 and Pr2 in the hysteresis characteristics of the ferroelectric capacitors represent the states of stored data “1” and “0”, respectively.
Then, as illustrated in
As can be seen from the above-mentioned operation, voltage caused in the bit line BL varies depending upon the amounts of remaining polarization for “1” data and “0” data as illustrated in
(Structure of Memory Cell Array 1a in Semiconductor Storage Device 100 in First Embodiment)
Referring now to
As illustrated in
As illustrated in
As illustrated in
The gate insulation layers 21 and the gate conductive layers 22 are sequentially laminated on the surface of the substrate 10. The gate insulation layers 21 and the gate conductive layers 22 are formed across the corresponding source/drain layers 11 at a certain pitch in a first direction orthogonal to a lamination direction. The first and second contact plug layers 23, 24 are formed to extend in the lamination direction from the top surfaces of the source/drain layers 11. The first and second contact plug layers 23, 24 are alternately formed at a certain pitch in the first direction. The contact layers 25 are formed on the top surfaces of the first contact plug layers 23. The interlayer insulation layers 26 are formed up to the top surfaces of the contact layers 25 (the second contact plug layers 24) so as to fill up the above-mentioned layers 21 to 25.
The gate insulation layers 21 are composed of silicon oxide (SiO2). The gate conductive layers 22 are composed of polysilicon. The first and second contact plug layers 23, 24 are composed of polycrystalline silicon doped with tungsten (W). The contact layers 25 are composed of, e.g., tungsten. The interlayer insulation layers 26 are composed of any one of BPSG (Boron Phosphorous Silicate Glass) and P-TEOS (Plasma-Tetra Ethoxy Silane).
In the above-mentioned configuration of the transistor layer 20, the gate insulation layers 21 and the gate conductive layers 22 function as cell transistors Tr together with the source/drain layers 11. In addition, the gate conductive layers 22 function as the control gate electrodes of the cell transistors Tr.
As illustrated in
The first conductive layers 31 are formed on the top surfaces of the respective contact layers 25. The ferroelectric layers 32 are formed on the top surfaces of the respective first conductive layers 31 in such a way that two ferroelectric layers 32 are formed on the first conductive layer 31 with a certain distance in the first direction from each other. The stopper layers 33 are formed on the top surfaces of the first conductive layers 31, i.e., they are formed in the same layer as the ferroelectric layers 32. The stopper layers 33 are formed in contact with the side surfaces of the ferroelectric layers 32. The second conductive layers are formed on the respective top surfaces of the ferroelectric layers 32 and the stopper layers 33.
The protection layer 35 is formed to cover the side surfaces of the first conductive layers 31, the side surfaces of the stopper layers 33, and both the side and top surfaces of the second conductive layers 34. The third contact plug layers 36 are formed to extend in the lamination direction from the top surfaces of the second contact plug layers 24 so as to penetrate the protection layer 35. The fourth contact plug layers 37 are formed to extend in the lamination direction from the top surfaces of the second conductive layers 34 so as to penetrate the protection layer 35. The interlayer insulation layers 38 are formed up to the respective top surfaces of the third and fourth contact plug layers 36 and 37 so as to fill up the above-mentioned layers 31 to 37.
The first conductive layers 31 and the second conductive layers 34 are configured to include any one of Pt, Ir, IrO2, SRO, Ru, and RuO2. The ferroelectric layers 32 include any one of lead zirconate titanate (PZT), strontium bismuth tantalate (SET), and bismuth ferrite (BFO).
The stopper layers 33 are configured to have a higher selection ratio under chemical mechanical polishing as compared with that of the ferroelectric layers 32. The stopper layers 33 are composed of, e.g., either alumina (Al2O3) or silicon nitride (SiN). The stopper layers 33 may also be composed of lamination of alumina and a noble metal film (such as Ir or Ot). The stopper layers 33 function as stoppers when planarizing and forming ferroelectric layers 32 by CMP, which will be described in detail below.
The protection layer 35 functions as a so-called hydrogen diffusion barrier layer. The protection layer 35 is composed of anyone of Al2O3, SiN, and TiO2. The third and fourth contact plug layers 36, 37 are composed of polycrystalline silicon doped with tungsten (W). The interlayer insulation layers 38 are composed of any one of P-TEOS, O3-TEOS, SGO, and Low-k layers (such as SiOF or SiOC).
In the above-mentioned configuration of the capacitor layer 30, the first conductive layers 31, the ferroelectric layers 32, and the second conductive layers 34 function as ferroelectric capacitors C.
As illustrated in
The first wiring layers 41 are composed of aluminum (Al) or copper (Cu). The interlayer insulation layer 42 is composed of any one of P-TEOS, O3-TEOS, SGO, and Low-k layers (such as SiOF or SiOC).
(First Manufacturing Process of Capacitor Layer 30 in First Embodiment)
Referring now to
Firstly, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Then, as illustrated in
Subsequent to
(Second Manufacturing Process of Capacitor Layer 30 in First Embodiment)
Referring now to
Firstly, as in the first manufacturing process, the steps of
For example, if the layer 31a is composed of a material having a heat conductivity higher than that of the layers 33a, then the surface temperature of the layer 31a may be higher than that of the layers 33a. This allows the layer 32a to be grown at a faster growing rate at the layer 31a having a higher surface temperature. In addition, the layer 31a may be composed of a material having a nucleation density higher than that of the layers 33a.
Subsequently, the same steps are performed as illustrated in
(Advantages of First Embodiment)
Advantages of the semiconductor storage device 100 according to the first embodiment will now be described below. As can be seen from the first embodiment described above, the capacitor layer 30 has the stopper layers 33 in the same layer as the ferroelectric layers 32. The stopper layers 33 have a selection ratio under chemical mechanical polishing that is higher than that of the ferroelectric layers 32. Due to the existence of the stopper layers 33, the top surfaces of the ferroelectric layers 32 are planarized with high accuracy when performing chemical mechanical polishing. That is, the semiconductor storage device 100 may suppress variations in the memory characteristics.
Referring now to
As such, the second manufacturing process A2 allows the layer 32aA to bear a smaller ratio to the layer 32aB than in the first manufacturing process A1 in an area AR that will eventually provide ferroelectric layers 32. That is, the second manufacturing process may suppress degradation in characteristics of the layer 32a (the ferroelectric layers 32) as compared with the first manufacturing process.
(Structure of Semiconductor Storage Device in Second Embodiment)
Referring now to
As illustrated in
The ferroelectric layer 32A has a side surface facing the stopper layer 33A, the side surface being formed in a forward-inclined shape with respect to the substrate 10 (generally trapezoidal shape with the bottom surface having a smaller length than that of the top surface). The stopper layer 33A has a side surface facing ferroelectric layer 32A, the side surface being formed in a backward-inclined shape with respect to the substrate 10. Note that in the second embodiment, the ferroelectric layers 32A are formed with the second manufacturing process of the first embodiment.
(Advantages of Second Embodiment)
Advantages of the semiconductor storage device according to the second embodiment will be described below. As in the first embodiment, the stopper layers 33A are formed in the same layer as the ferroelectric layers 32A. Accordingly, the semiconductor storage device of the second embodiment has the same advantages as the first embodiment.
Referring now to
(Structure of Semiconductor Storage Device in Third Embodiment)
Referring now to
As illustrated in
As illustrated in
(Advantages of Third Embodiment)
Advantages of the semiconductor storage device according to the third embodiment will be described below. As in the first and second embodiments, the stopper layers 33B are formed in the same layer as the ferroelectric layers 32B. Accordingly, the semiconductor storage device of the third embodiment has the same advantages as the first and second embodiments.
While embodiments of the present invention have been described, the present invention is not intended to be limited to the disclosed embodiments, and various other changes, additions or the like may be made thereto without departing from the spirit of the invention.
For example, according to the first embodiment, the memory cell array 1a has the stopper layers 33. However, in the step of
In addition, while the semiconductor storage device according to the first and second embodiments mentioned above has been described as TC parallel unit serial connection type FeRAM, it may also be utilized in 1T type (transistor type), 1T1C type (capacitor type), or 2T2C type FeRAM applications.
Number | Date | Country | Kind |
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2008-289357 | Nov 2008 | JP | national |