SEMICONDUCTOR STORAGE DEVICE

Abstract

According to one embodiment, a semiconductor storage device includes a first electrode and a second electrode spaced in a first direction and a phase change layer provided between the first electrode and the second electrode. The phase change layer comprises at least one of germanium (Ge), antimony (Sb), and tellurium (Te). The phase change layer is configured to be able to transition to a first state in which a volume ratio of an amorphous phase to a crystalline phase is a first ratio, a second state in which the volume ratio is a second ratio larger than the first ratio, and a third state in which the volume ratio is a third ratio larger than the second ratio.

Description

Claims

1. A semiconductor storage device, comprising: a first electrode and a second electrode separated in a first direction; anda phase change layer between the first electrode and the second electrode and comprising at least one of germanium (Ge), antimony (Sb), and tellurium (Te), wherein the phase change layer is configured to be able to transition to a first state in which a volume ratio of an amorphous phase to a crystalline phase is a first ratio, a second state in which the volume ratio is a second ratio larger than the first ratio, and a third state in which the volume ratio is a third ratio larger than the second ratio.

2. The semiconductor storage device according to claim 1, wherein the phase change layer includes a first region and a second region closer to the first electrode than the first region, anda volume ratio of the amorphous phase to the crystalline phase in the second region is smaller than a volume ratio of the amorphous phase to the crystalline phase in the first region when the phase change layer is in the second state.

3. The semiconductor storage device according to claim 1, wherein a width of the first electrode in the first direction is smaller than 10 nm.

4. The semiconductor storage device according claim 1, wherein the phase change layer contains 10% to 90% of the crystalline phase with respect to the total volume of the phase change layer in the second state.

5. The semiconductor storage device according to claim 1, wherein, when a width of the phase change layer in the first direction is a first width and a width of the phase change layer in a second direction intersecting the first direction is a second width, the first width is at least 1.5 times the second width.

6. The semiconductor storage device according to claim 1, wherein the phase change layer transitions from the first state to the second state by application of a first voltage, andthe phase change layer transitions from the first state to the third state by application of a second voltage larger than the first voltage.

7. The semiconductor storage device according to claim 6, wherein the phase change layer transitions from the second state to the first state by application of a third voltage at a first time, and then application of a fourth voltage smaller than the third voltage at a second time, andthe phase change layer transitions from the second state to the third state by application of a fifth voltage larger than the third voltage.

8. The semiconductor storage device according to claim 7, wherein the phase change layer transitions from the third state to the first state by application of a sixth voltage at a third time, and then application of a seventh voltage smaller than the sixth voltage at a fourth time, andthe phase change layer transitions from the third state to the second state by application of a voltage that monotonically increases from an eighth voltage to a ninth voltage larger than the eighth voltage from the fifth time to a sixth time, and then application of the ninth voltage from the sixth time to a seventh time.

9. The semiconductor storage device according to claim 1, wherein a positive voltage is applied to the first electrode in a read operation and a write operation.

10. The semiconductor storage device according to claim 1, further comprising: a first wiring extending in a third direction intersecting the first direction; anda second wiring extending in a fourth direction intersecting the first direction and the third direction, wherein the first electrode and the second electrode are provided between the first wiring and the second wiring.

11. A memory device, comprising: a word line;a bit line separated from the word line in a first direction;a memory cell between the word line and the bit line in the first direction, the memory cell including: an anode electrode contacting the word line;a variable resistance element contacting the anode electrode, the anode electrode being between the variable resistance element and the word line in the first direction;a conductor layer contacting the variable resistance element, the variable resistance element being between the anode electrode and the conductor layer in the first direction;a switch element contacting the conductor layer, the conductor layer being between the switch element and the variable resistance element in the first direction; anda cathode electrode between the switch element and the bit line, wherein the variable resistance element comprises a first region and a second region, the first region being closer to the conductor layer than is the second region,the variable resistance element has a high resistance state in which a volume ratio of the variable resistance element is greater than 90% amorphous phase, a low resistance state in which the volume ratio is greater than 90% crystalline phase, and an intermediate resistance state in which the volume ratio is between 10% and 90% crystalline phase,a volume ratio of the first region is greater than 90% amorphous in the intermediate resistance state, anda volume ratio of the second region is less than 90% amorphous in the intermediate state.

12. The memory device according to claim 11, wherein the first region has a different composition from the second region.

13. The memory device according to claim 11, wherein the first and second regions are a Ge—Sb—Te based chalcogenide compound, andthe amount of tellurium in the first region is less than the amount of tellurium in the second region.

14. The memory device according to claim 11, wherein the variable resistance element includes a phase change layer, anda ratio of the length of the phase change layer in the first direction to a width of the phase change layer in a second direction perpendicular the first direction is at least 1.5:1.

15. The memory device according to claim 14, wherein the phase change layer is a Ge—Sb—Te based chalcogenide compound.

16. The memory device according to claim 14, wherein a thickness of the first electrode in the first direction is less than 10 nm.

17. The memory device according to claim 11, wherein a thickness of the first electrode in the first direction is less than 10 nm.

18. A semiconductor storage device, comprising: a first electrode and a second electrode separated in a first direction; anda phase change layer between the first electrode and the second electrode, wherein the phase change layer is configured to be able to transition to a first state in which a volume ratio of an amorphous phase to a crystalline phase is a first ratio, a second state in which the volume ratio is a second ratio larger than the first ratio, and a third state in which the volume ratio is a third ratio larger than the second ratio.

19. The semiconductor storage device according to claim 18, wherein the phase change layer includes a first region and a second region closer to the first electrode than the first region, anda volume ratio of the amorphous phase to the crystalline phase in the second region is smaller than a volume ratio of the amorphous phase to the crystalline phase in the first region when the phase change layer is in the second state.

20. The semiconductor storage device according to claim 19, wherein the phase change layer is a Ge—Sb—Te based chalcogenide compound with a first region having a higher tellurium concentration than a second region.