BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1-5 show manufacturing processes in accordance with the invention;
FIG. 6 shows a final processing step in accordance with the invention, in addition to a final structure;
FIGS. 7-11 show alternative manufacturing processes in accordance with the invention; and
FIG. 12 shows a final processing step in accordance with the invention, in addition to a final structure.
DETAILED DESCRIPTION OF THE EMBODIMENTS OF THE INVENTION
FIG. 1 shows a beginning structure in accordance with the invention. In this beginning structure, a SOI 12 is embedded in a substrate 10. The substrate may be BOX. A gate oxide layer 14, for example, is blanket grown onto the SOI 12 and optionally on the substrate 10 using any conventional method such as, for example, without limiting the scope of the invention, thermally grown oxide with nitrogen enrichment or chemical vapor deposition processes. These chemical vapor deposition processes may include low-pressure chemical vapor deposition (LPCVD) or, if the desired gate oxide necessitates, metal organic CVD (MOCVD).
The gate oxide layer 14 can comprise any appropriate metal oxide material. The gate oxide layer 14 is, in embodiments, determined by the desired capacitance of the gate using a high dielectric constant (k) material with low dielectric leakage current, for example. In embodiments, the gate oxide layer may be exchanged with a nitride layer or other appropriate material such as, for example, silicon oxide. In further embodiments, the gate layer 14 can comprise a thickness between approximately 0.5 nm to 3 nm. However, the thickness of the gate oxide layer 14 may vary depending on any number of known parameters such as the gate oxide material, itself. Therefore, in view of the various factors for generating a desired capacitance, thickness outside the above-described region are equally contemplated by the invention.
Still referring to FIG. 1, a gate 16 is formed at any desired location on the gate oxide layer 14 above the SOI region 12. The gate 16 can comprise any appropriate material. In embodiments, the gate 16 is made of polysilicon; however, based on device performance and the gate oxide material, the gate material can be of any material necessary to warrant the desired performance. For example, if a gate oxide material has a dielectric constant higher than the dielectric constant of silicon dioxide (high-k material), then a gate can be made of more compatible material including metals. The gate 16 is capped by a protective barrier layer 18 which can be made of any material used for protecting parts of a semiconductor device such as, for example, nitride material.
FIG. 2 shows further process steps in accordance with the invention. As shown in FIG. 2, excess material from the gate oxide layer 14, not covered by the gate 16, is removed during this processing step. During this stage of processing, an undercut is formed under the gate 16. Any conventional method can be used to remove portions of the gate oxide layer 14 including isotropic and anisotropic methods or any dry or wet methods. In embodiments, the removal process is chosen based on the type and thickness of the gate oxide. In embodiments, for example, if the gate oxide is silicon oxide, the removal process can include using hydrogen fluoride in any form, such as gas, liquid, solution, in mixture with other agents, buffered, diluted or anhydrous.
In embodiments, an isotropic etching leads to lateral removal of material underneath the gate 16 causing an undercut. Such undercut underneath the gate 16 can reach dimensions of up to 5 nm per side.
FIG. 3 shows further process steps in accordance with the invention. In this processing step, a protective barrier material such as nitride is formed on the sidewalls of the gate 16 to form a protective layer 20. The protective barrier material also covers exposed portions of the gate oxide layer 14 in the undercut underneath the gate 16. The protective layer 20 can be formed in any conventional manner, known to those of skill in the art such as, for example, nitride deposition processes such as plasma enhanced chemical vapor deposition (PECVD) or rapid thermal chemical vapor deposition (RTCVD).
As shown in FIG. 3, the gate stack is completely enclosed by the protective barrier layers 18 and 20, in addition to the SOI material 12. In this manner, the sealed structure is now protected from any further processing steps, as described in greater detail below. Thus, during subsequent cleaning steps, the gate oxide layer will not be exposed to etchant chemistries, thus ensuring that the gate oxide layer will remain intact. This, in turn, ensures that the gate, itself, will not become exposed during subsequent steps, thus preventing short circuits in the device.
In embodiments, the sidewalls which are formed from the protective layer 20 do not require added thickness to avoid undercut erosion of the gate oxide 12 in subsequent processing steps. This is due to the fact that the protective barrier 20 is provided within the undercut, as compared to conventional methods which do not have any protective material within the undercut. Thus, in the case of this embodiment, the sidewalls formed from the protective layer 20 can be 10 nm or less in thickness and, even with this thickness, under gate erosion can be avoided. This will prevent shorts from occurring in subsequent processing steps.
Also, it is important to note that since the gate stack is now completely enclosed, no additional material, e.g., precautionary thickness for the sidewalls, is necessary to prevent gate oxide corrosion and gate undercut. Thus, the thickness of the sidewalls can be reduced to the minimum necessary for protecting the gate stack from exposure to any subsequent process steps. This in turn, also reduces the distance between the gate oxide and the source and drain regions.
FIG. 4 shows additional process steps in accordance with the invention. In these processing steps, etching is performed to form the source and drain (S/D) wells 21. The formation of the source and drain wells 21 can be accomplished using anisotropic etching such as RIE. As is shown in FIG. 4, there is a difference between the gate length (well to well distance) and the transistor length (length of gate oxide in contact with SOI). This difference is approximately two times the sidewall thickness of the protective layer 20 at the level of the gate oxide 12. However, this distance is significantly decreased, compared to conventional structures and methods, since the protective layer 20 is 10 nm or less at the sidewalls, owing to the manufacturing processes described herein. Thus, applying the present method, the length of the gate oxide can be increased by approximately 0.2 nm or more by selecting an appropriate sidewall 20 thickness. In this manner, transistor efficiency is substantially increased over that of the known art.
FIG. 5 shows further process steps in accordance with the invention. In FIG. 5, the source and drain wells 21 are filled with epitaxial material 22. In embodiments, the source and drain wells 21 are filled with SiGe that is epitaxially grown. By filling the source and drain wells 21 with SiGe, the device may be placed in a compressive strain which is preferred for a PFET device. Although this embodiment exemplifies the aspects of the invention with use of a PFET device, it is obvious that the same method can be used during the manufacture of a NFET device or both, e.g., CMOS devices. In embodiments, the SiGe composition can be of various different ratios, e.g., the atomic Ge content can be between 0.1 and 50 atomic %, preferably between 1 and 40 atomic %, and more preferably between 5 and 30 atomic %.
FIG. 6 shows another processing step of the invention, in addition to a final structure. In the processing step of FIG. 6, the protective layer 20 is removed using any conventional method known to those of skill in the art. As shown, using the processes described herein, and more particularly, the protective layer 20, the gate 16 and gate oxide layer 14 remain separated from the source and drain material thus preventing any shorts from occurring in the device.
It is noted that the device performance increases using the fabrication method of the invention. For example, shorting of the device is prevented. In addition, the eSiGe grown source/drain edge can be closer to the transistor channel, improving transistor performance.
FIGS. 7-12 show an alternative method of fabricating a structure in accordance with the invention. FIGS. 7-9 show the same processing steps as described with reference to FIGS. 1-3. By way of example, FIG. 7 shows a beginning structure in accordance with the invention. In this beginning structure, a SOI 12 is embedded in a substrate 10. A gate oxide layer 14 is blanket grown onto the SOI 12 and optionally on the substrate 10 using any conventional method as described above. The gate oxide material can comprise any appropriate metal oxide material including silicon oxide and can comprise a thickness between approximately 0.1 nm and 7 nm.
Still referring to FIG. 7, a gate 16 is formed at any desired location on the gate oxide layer 14 above the SOI region 12. The gate 16 can comprise any appropriate material such as of polysilicon. However, based on device performance and the desired gate oxide material, the gate material can be of any appropriately known material to warrant the desired performance, as describe with reference to FIG. 1.
As shown in FIG. 8, excess gate oxide material 14, not covered by the gate 16, is removed using any conventional processing. In embodiments, an isotropic method leads to lateral removal of material underneath the gate 16 resulting in an undercut under the gate 16. Such undercut underneath the gate 16 can reach dimensions of up to 5 nm per side.
FIG. 9 shows further process steps in accordance with the invention. In these processing steps, a protective layer 20 is formed on the sidewalls of the gate 16. As with FIG. 3, the protective layer 20 also covers exposed portions of the gate oxide layer 14 in the undercut underneath the gate 16. The gate stack is now completely enclosed by the protective barrier material layers 18 and 20, in addition to the SOI 12. In this manner, the sealed structure is now protected from any further processing steps. The protective layer 20 can be formed in any conventional manner, known to those of skill in the art.
As in the previous embodiment described above, the sidewalls formed from the protective layer 20 do not require added thickness to avoid undercut erosion in subsequent processing steps. This is due to the protective layer 20 being provided within the undercut thus protecting the oxide layer from any corrosion. In the case of this embodiment, the thickness of the sidewalls formed from the protective layer 20 can be significantly minimized to about 10 nm or less in thickness and, again, gate erosion can be avoided. This will prevent shorts from occurring in subsequent processing steps.
Thus, as with the previous embodiment, since the gate stack is now completely enclosed, no additional material, e.g., precautionary thickness for the sidewalls, is necessary to prevent gate oxide corrosion and gate undercut. Thus, the thickness of the sidewalls can be reduced to the minimum necessary for protecting the gate stack from exposure to any subsequent process steps.
FIG. 10 shows alternative processing steps in accordance with the invention. An isotropic etching process is used to form the source and drain wells 21. As is shown in FIG. 10, although the isotropic etching causes an undercut under the gate 16, the protective layer 20 remains intact, protecting the gate oxide layer 14 from being eroded. This will prevent any future shorting of the device. More specifically, this will prevent the corrosion of the oxide layer 14 from reaching beyond the gate 16, thus avoiding exposure of the gate material.
In FIG. 11, the source and drain wells 21 are filled with material 22, similar to that described with reference to FIG. 5. Here, again, the material can be any material suitable for achieving the desired device performance. Also, further process steps to implement the invention.
Still referring to FIG. 11, the processes described herein and more particularly the use of the isotropic etching process in combination with the protective layer 20, results in the gate and the source and drain regions approaching extreme proximity. More specifically, the source and drain regions are formed under the gate 16, beyond at least a portion or outer edge of the undercut. Thus, using the methods described herein produces devices with improved performance, while preventing any shorting from occurring.
FIG. 12 shows the device after the removal of the protective material 20. As described with reference to FIG. 6, the gap can further be filled with material to improve device performance, such as gate oxide.
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
While the invention has been described in terms of embodiments, those skilled in the art will recognize that the invention can be practiced with the modification within the spirit and scope of the appended claims. For example, the invention can be readily applicable to bulk substrates.
Patent Application
20080057673
