Etching is a technology commonly used in a semiconductor structure manufacturing method. Etching is a main process of patterning associated with photolithography. Photoetching means first lithographically exposing a photoresist by photolithography and then corroding a to-be-removed portion by other means.
The present application relates to the field of semiconductors, and in particular, to a semiconductor structure manufacturing method and a semiconductor structure manufacturing device.
Various embodiments of the present application provide a semiconductor structure manufacturing method, including: providing a substrate; forming a patterned photoresist layer on the substrate, and etching the substrate by using the patterned photoresist layer as a mask; performing, by using a plasma asher, plasma ashing treatment on the patterned photoresist layer and residues produced by etching after the substrate is etched; and performing the plasma ashing treatment in an oxygen-free environment.
The embodiments of the present application further provide a semiconductor structure manufacturing device, adapted to perform plasma ashing treatment on residues on a semiconductor structure, the semiconductor structure including a substrate, the semiconductor structure manufacturing device including: a chuck and at least three support pillars; the chuck being configured to provide a heat source; the support pillar being located on the chuck, and the support pillar being configured to bear the substrate and detach the substrate from the chuck.
One or more embodiments are exemplarily described by using figures that are corresponding thereto in the accompanying drawings; the exemplary descriptions do not constitute limitations on the embodiments. Elements with same reference numerals in the accompanying drawings are similar elements. Unless otherwise particularly stated, the figures in the accompanying drawings do not constitute a scale limitation.
It can be known from the Background that, in a process of removing residues produced by etching, it is not easy to remove the residues thoroughly, and it is easy to produce new residues, thereby affecting the quality of a semiconductor structure.
In order to solve the above problem, an embodiment of the present application provides a semiconductor structure manufacturing method, including: performing, by using a plasma asher, plasma ashing treatment on a patterned photoresist layer and residues produced by etching after a substrate is etched; and performing the plasma ashing treatment in an oxygen-free environment. In the oxygen-free environment, the plasma ashing treatment can not only remove an original oxide layer, but also prevent production of new residues, so as to ensure that the semiconductor structure has good electrical properties.
In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, various embodiments of the present application will be described below in details with reference to the drawings. However, those of ordinary skill in the art may understand that, in the embodiments of the present application, numerous technical details are set forth in order to enable a reader to better understand the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and various changes and modifications based on the embodiments below.
Referring to
In one embodiment, the first dielectric layer 12 is made of an insulation material such as silicon dioxide. In other embodiments, the first dielectric layer may also be made of silicon nitride, silicon carbonitride or silicon oxycarbide.
In one embodiment, the first metal layer 11 is made of a material with a lower resistivity, such as copper. In other embodiments, the first metal layer may also be made of tungsten, tantalum or titanium.
In one embodiment, the second dielectric layer 13 is made of an insulation material such as silicon dioxide. In other embodiments, the second dielectric layer may also be made of silicon nitride, silicon carbonitride or silicon oxycarbide.
A patterned photoresist layer 16 is formed on the substrate 14. For example, a photoresist layer is applied to the substrate 14, and the photoresist layer is exposed. The exposed photoresist layer may be treated with a solvent, so as to remove part of a photoresist to form the patterned photoresist layer 16.
Referring to
In this embodiment, the second dielectric layer 13 is etched by using the patterned photoresist layer 16 as a mask to form a via 17 located in the second dielectric layer 13, so as to expose the first metal layer 11.
In one embodiment, part of the second dielectric layer 13 is removed by dry etching. An etching gas may be carbon tetrafluoride, trifluoromethane or oxygen. Since the etching gas is oxidizing, residues such as an oxide layer 15 may be produced on the first metal layer 11. In other embodiments, part of the second dielectric layer may also be removed by wet etching.
Referring to
The plasma ashing treatment in the oxygen-free environment can prevent further thickening of the oxide layer 15 (refer to
A reaction gas 23 is introduced during the plasma ashing treatment. The reaction gas 23 includes H2N2 or NH3. H2N2 or NH3 having certain reducibility, which can further remove residual oxides on the first metal layer 11 and can also prevent production of new oxides on the first metal layer 11. In addition, H2N2 or NH3 is less corrosive and may not cause great damages to the first dielectric layer 12 and the second dielectric layer 13.
In one embodiment, a flow rate of H2N2 is 3000 sccm to 10000 sccm, which may be, for example, 4000 sccm, 5000 sccm or 8000 sccm. When the flow rate of H2N2 is in the above range, process time can be shortened to some extent and damages to the semiconductor structure can also be prevented.
In yet another embodiment, a flow rate of NH3 is 1000 sccm to 10000 sccm, which may be, for example, 2000 sccm, 4000 sccm or 7000 sccm. When the flow rate of NH3 is in the above range, process time can be shortened to some extent and damages to the semiconductor structure can also be prevented.
In one embodiment, the reaction gas 23 further includes nitrogen during the plasma ashing treatment. Nitrogen, as an inactive gas, can improve hardness and wear resistance of the semiconductor structure to some extent. In addition, plasma produced by nitrogen has a strong bombardment on a surface of the semiconductor structure, so nitrogen can also improve an ashing effect, so as to increase cleanliness of the semiconductor structure.
During the plasma ashing treatment, a chamber temperature is lower and is in a range of 50° C. to 250° C., which can be, for example, 100° C., 110° C., 120° C., 150° C. or 200° C. It may be understood that if the chamber temperature is higher, oxygen atoms in the oxide layer 15 (refer to
In one embodiment, a chamber pressure is in a range of 50 mtorr to 2000 mtorr during the plasma ashing treatment, which may be, for example, 100 mtorr, 500 mtorr or 1000 mtorr. When the chamber pressure is in the above range, the efficiency of ashing treatment can be improved. The lower the pressure is, the less a metal surface is oxidized.
In one embodiment, radio frequency power is 1000 W to 5000 W during the plasma ashing treatment, which may be, for example, 2000 W, 3000 W or 4000 W. When the radio frequency power is in the above range, energy of the plasma can be increased, so as to increase degrees of ashing of the photoresist and the oxide.
That is, the support pillar 21 lifts the substrate 14, which can prevent direct contact between the substrate 14 and the chuck 22, so as to reduce a heating rate of the substrate 14. A lower temperature rise speed can reduce a degree of diffusion of the oxygen atoms in the oxide layer 15 (refer to
In one embodiment, the support pillar is configured to bear the substrate and detach the substrate from the chuck. That is, the support pillar can prevent direct contact between the chuck and the substrate, so as to reduce a temperature rise rate of the substrate, reduce oxidation capacity of a surface of a metal layer, prevent formation of an additional oxide layer to resist electrical conductivity of metal, and reduce a degree of diffusion of oxygen atoms in the oxide layer towards a first metal layer, so that the semiconductor structure has good electrical properties.
In the process of providing the heat source by the chuck 22, a temperature variation process of the substrate 14 includes a temperature rise stage and a constant temperature stage. It is to be noted that, in the temperature rise stage, the oxide layer 15 (refer to
Main reasons for controlling a removal process of the oxide layer 15 (refer to
A height of the support pillar 21 in the temperature rise stage is greater than that in the constant temperature stage. It may be understood that if the height of the support pillar 21 is higher in the temperature rise stage, heat received by the substrate 14 may be reduced, and then the probability of diffusion of the oxygen atoms is reduced; if the height of the support pillar 21 is lower in the constant temperature stage, the heat received by the substrate 14 may be increased, so as to ensure that the substrate 14 has a higher temperature to speed up the ashing process of the patterned photoresist layer 16, improve the efficiency and reduce costs.
In one embodiment, in the temperature rise stage, the height of the support pillar 21 decreases gradually in a direction perpendicular to an upper surface of the chuck 22. In the constant temperature stage, the height of the support pillar 21 remains constant in the direction perpendicular to the upper surface of the chuck 22. Main reasons are as follows. At the beginning of the temperature rise stage, that is, when the chuck 22 just starts to provide the heat source, a degree of temperature variation of the substrate 14 is great; with the continuous heating of the chuck 22, the degree of temperature variation of the substrate 14 decreases gradually. At the beginning of the temperature rise stage, the support pillar 21 has a higher height, which can decrease the degree of temperature variation of the substrate 14. With the constant rise of the temperature, the height of the support pillar 21 decreases gradually, which can ensure that the substrate 14 can reach a preset temperature quickly, thereby shortening the time of plasma ashing treatment of the photoresist.
In the temperature rise stage, a temperature rise rate of the substrate 14 is 5° C./s to 20° C./s, which may specifically be 8° C./s, 12° C./s or 18° C./s. When the temperature rise rate is in the above range, the degree of diffusion of the oxygen atoms can be reduced, and the oxide layer 15 can be ensured to be more thoroughly removed.
In addition, the height of the support pillar 21 in the direction perpendicular to the upper surface of the chuck 22 may be 3 mm to 20 mm, which may specifically be 8 mm, 12 mm or 18 mm. When the height of the support pillar 21 is in the above range, it can be ensured that the substrate 14 can have a more appropriate heating rate, so that a diffusion rate of the oxygen atoms in the oxide layer 15 can be reduced, and the time of the plasma ashing treatment can also be reasonably controlled.
In other embodiments, the height of the support pillar may also remain unchanged.
In one embodiment, four support pillars 21 are provided. The four support pillars 21 can improve stability of placement of the substrate 14. In other embodiments, three or four or more support pillars may also be provided.
In one embodiment, the plurality of support pillars 21 may be equidistant from a central axis of the chuck 22. In this way, after the substrate 14 is placed on the support pillar 21, the substrate 14 can be subjected to a more uniform force, thereby improving the stability of the substrate 14.
In one embodiment, the support pillar 21 may consist of a plurality of sleeve rods nested in sequence. When the sleeve rod extends, the height of the support pillar 21 is increased. When the sleeve contracts, the height of the support pillar 21 is reduced. In other embodiments, a push rod may also be arranged inside the support pillar, and expansion of the push rod can control the rise or fall of the support pillar.
In one embodiment, the support pillar 21 is made of ceramic. Due to low thermal conductivity of the ceramic, rapid transfer of heat by the chuck 22 to the substrate 14 through the support pillar 21 can be prevented. In this way, the temperature rise rate of the substrate 14 can be reduced to reduce the diffusion rate of the oxygen atoms, thereby preventing an increase in the resistance of the first metal layer 11. In other embodiments, the support pillar may also be made of metals with low thermal conductivity.
Referring to
The SO3 gas is anhydrous, and during the introduction, the chamber temperature is lower. It is difficult for the anhydrous SO3 gas at a low temperature to oxidize the first metal layer 11. Therefore, no new oxide impurities may be produced during the above treatment, nor may the electrical properties of the first metal layer 11 be adversely affected.
The semiconductor structure is cleaned using a mixed solution of dilute sulfuric-peroxide-HF (DSP) and a dilute HF (DHF) solution. The above solution can further remove impurities such as oxides and inorganic matters.
In the DSP solution, H2O2 has a mass concentration of 1 wt % to 5 wt %; H2SO4 has a mass concentration of 1 wt % to 10 wt %; and HF has a mass concentration of 0.01 wt % to 0.08 wt %. When the concentration of each component is in the above range, the impurities can be thoroughly removed, and damages to the semiconductor structure can also be prevented.
In the DHF solution, HF: H2O=1:100 to 1:2000. When the concentration of each component is in the above range, cleanliness of the semiconductor structure can be improved, and damages to the semiconductor structure can also be prevented.
It is to be noted that, since Ammonia Peroxide Mix (APM) is not used in this embodiment, the first metal layer 11 and a second metal layer 19 may not be damaged.
The second metal layer 19 is formed on the first metal layer 11. The second metal layer 19 further fills the via 17 (refer to
Since the oxide layer 15 on the surface of the first metal layer 11 is more thoroughly removed, the first metal layer 11 and the second metal layer 19 have low series resistance, and the semiconductor structure has better electrical properties.
The first metal layer 11 is made of low resistance metals such as copper, tungsten, titanium, gold, tantalum or silver, so that the resistance of the semiconductor structure can be reduced and operating efficiency of the semiconductor structure can be improved.
Based on the above, in this embodiment, the patterned photoresist layer 16 and impurities such as the residual oxide layer 15 are ashed in the oxygen-free environment, which enables the oxide layer 15 to be more thoroughly removed without producing new residues. In addition, the support pillar 21 is used to lift the substrate 14, which can avoid the direct contact between the chuck 22 and the substrate 14, so as to reduce the temperature rise rate of the substrate 14 and prevent an affection of the electrical properties of the semiconductor structure caused by diffusion of the oxygen atoms in the oxide layer 15 into the first metal layer 11.
Another embodiment of the present application provides a semiconductor structure manufacturing device. The semiconductor structure manufacturing device is adapted to perform plasma ashing treatment on residues on a semiconductor structure.
Contents in this embodiment the same as or similar to those in the first embodiment can be obtained with reference to the first embodiment, which are not described in detail herein.
Referring to
In one embodiment, in the process of providing the heat source by the chuck 22, a temperature variation process of the substrate 14 includes a temperature rise stage and a constant temperature stage. It is to be noted that, in the temperature rise stage, the oxide layer 15 and the patterned photoresist layer 16 (refer to
Main reasons for controlling a removal process of the oxide layer 15 and the patterned photoresist layer 16 in stages are as follows. At a lower temperature, the oxygen atoms in the oxide layer 15 diffuse slowly, which has little effect on the resistance of the first metal layer 11. In the temperature rise stage, the substrate 14 is at a lower temperature; therefore, complete removal of the oxide layer 15 in this stage can prevent violent diffusion of oxygen atoms in the subsequent constant temperature stage. In the constant temperature stage, the substrate 14 is at a higher temperature, which can speed up the removal of the patterned photoresist layer 16, thereby shortening the process time.
A height of the support pillar 21 in the temperature rise stage is greater than that in the constant temperature stage. It may be understood that if the height of the support pillar 21 is higher in the temperature rise stage, heat received by the substrate 14 may be reduced, and then the probability of diffusion of the oxygen atoms is reduced; if the height of the support pillar 21 is lower in the constant temperature stage, the heat received by the substrate 14 may be increased, so as to ensure that the substrate 14 has a higher temperature to speed up the ashing process of the patterned photoresist layer 16.
In one embodiment, in the temperature rise stage, the height of the support pillar 21 decreases gradually in a direction perpendicular to an upper surface of the chuck 22. In the constant temperature stage, the height of the support pillar 21 remains constant in the direction perpendicular to the upper surface of the chuck 22. Main reasons are as follows. At the beginning of the temperature rise stage, that is, when the chuck 22 just starts to provide the heat source, a degree of temperature variation of the substrate 14 is great; with the continuous heating of the chuck 22, the degree of temperature variation of the substrate 14 decreases gradually. At the beginning of the temperature rise stage, the support pillar 21 has a higher height, which can decrease the degree of temperature variation of the substrate 14. With the constant rise of the temperature, the height of the support pillar 21 decreases gradually, which can ensure that the substrate 14 can reach a preset temperature quickly, thereby shortening the time of plasma ashing treatment of the photoresist.
A temperature rise rate of the substrate 14 is 5° C./s to 20° C./s in the temperature rise stage. When the temperature rise rate is in the above range, a degree of diffusion of the oxygen atoms can be reduced, and the oxide layer 15 can be ensured to be more thoroughly removed.
In addition, the height of the support pillar 21 in the direction perpendicular to the upper surface of the chuck 22 may be 3 mm to 20 mm. When the height of the support pillar 21 is in the above range, it can be ensured that the substrate 14 can have a more appropriate heating rate, so that a diffusion rate of the oxygen atoms in the oxide layer 15 can be reduced, and the time of the plasma ashing treatment can also be reasonably controlled.
In yet other embodiment, the height of the support pillar may also remain unchanged.
In one embodiment, four support pillars 21 are provided. The four support pillars 21 can improve stability of placement of the substrate 14. In other embodiments, three or four or more support pillars may also be provided.
In addition, the plurality of support pillars 21 may be equidistant from a central axis of the chuck 22. In this way, after the substrate 14 is placed on the support pillar 21, the substrate 14 can be subjected to a more uniform force, thereby improving the stability of the substrate 14.
In one embodiment, the support pillar 21 may consist of a plurality of sleeve rods nested in sequence. When the sleeve rod extends, the height of the support pillar 21 is increased. When the sleeve contracts, the height of the support pillar 21 is reduced. In other embodiments, a push rod may also be arranged inside the support pillar, and expansion of the push rod can control the rise or fall of the support pillar.
In one embodiment, the support pillar 21 is made of ceramic. Due to low thermal conductivity of the ceramic, rapid transfer of heat by the chuck 22 to the substrate 14 through the support pillar 21 can be prevented. In this way, the temperature rise rate of the substrate 14 can be reduced to reduce the diffusion rate of the oxygen atoms, thereby preventing an increase in the resistance of the first metal layer 11. In other embodiments, the support pillar may also be made of metals with low thermal conductivity.
Based on the above, the semiconductor structure manufacturing device according to this embodiment includes a chuck 22 and a plurality of support pillars 21 located on the chuck 22. The plurality of support pillars 21 may support the substrate 14 to prevent direct contact between the substrate 14 and the chuck 22, so as to reduce a heating degree of the substrate 14 and reduce a degree of diffusion of impurity atoms such as oxygen atoms on the substrate 14, thereby ensuring good electrical properties of the semiconductor structure.
Those of ordinary skill in the art may understand that the above implementations are specific embodiments for implementing the present application. However, in practical applications, various changes in forms and details may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.
Number | Date | Country | Kind |
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202110043371.8 | Jan 2021 | CN | national |
This is a continuation of International Patent Application No. PCT/CN2021/110077 filed on Aug. 2, 2021, which claims priority to Chinese Patent Application No. 202110043371.8 filed on Jan. 13, 2021. The disclosures of the above-referenced applications are incorporated herein by reference in their entirety.
Number | Date | Country | |
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Parent | PCT/CN2021/110077 | Aug 2021 | US |
Child | 17453850 | US |