Patent Application
20230025767
The present application is a non-provisional patent application claiming priority to European Patent Application No. 21187116.5, filed on Jul. 22, 2021, the contents of which are hereby incorporated by reference.
The present disclosure relates to the fabrication of back-side contacts on a back-side of a (e.g., thin) semiconductor layer, wherein the semiconductor layer also comprises front-side logic devices arranged on its front-side. The disclosure presents, in particular, a semiconductor structure that includes the semiconductor layer, the front-side logic devices, and the back-side contacts. The back-side contacts are formed in an epitaxial layer stack of four or more epitaxial layers. The disclosure also provides a device, which includes the semiconductor structure and additionally back-side semiconductor devices coupled to the back-side contacts of the semiconductor structure.
Extreme thinning of a semiconductor substrate (or layer), for instance, using an etch stop layer, may be explored to fabricate back-side semiconductor devices on the semiconductor substrate. For instance, this technique may be used to fabricate a back-side Power Distribution Network (PDN) for front-side logic devices, wherein the PDN includes the back-side semiconductor devices. The technique opens up many new system and processing possibilities.
Finally,
While fabricating the back-side semiconductor devices 16 in this way is an option, there can be also many difficulties. For instance, as also shown in
For instance, one approach is to define these back-side contacts 17 through the front-side of the silicon layer 13, for instance, by a front-side implantation. This approach may be used as an attempt to circumvent a limit of the thermal budget for the back-side contacts 17. However, at least two problems can arise with this approach.
Firstly, any front-side implanted dopants will spread out laterally, hence, they may create a punch-through path that shorts any source and/or drain terminals of the back-side contacts 17. Secondly, the silicon substrate 11 can deform during the thinning process, and also during a later bonding process. This can induce an overlay between the back-side contacts 17 formed by front-side implantation and the back-side semiconductor devices 16. The overlay can again cause a significant deterioration of the source and/or channel series resistances.
In view of the above-mentioned challenges and disadvantages, embodiments of this disclosure aim to provide a new approach for fabricating back-side contacts on a back-side of a semiconductor layer. The back-side contacts can be suitable for coupling to one or more back-side semiconductor devices (e.g., back-side logic devices) arranged on the back-side of the semiconductor layer. Further, the back-side contacts can be able to connect the back-side semiconductor devices to one or more front-side logic devices arranged at a front-side of the semiconductor layer. For instance, it could be possible to use the back-side semiconductor devices to be part of a PDN for the front-side logic devices.
A first aspect of this disclosure provides a semiconductor structure comprising: a semiconductor layer; one or more front-side logic devices, which are at least partly arranged in a front-side of the semiconductor layer; at least four epitaxial layers arranged on a back-side of the semiconductor layer, wherein the four epitaxial layers comprise a first epitaxial layer of a first conductivity type, a second epitaxial layer of a second conductivity type provided directly on the first epitaxial layer, a third epitaxial layer of the second conductivity type provided directly on the second epitaxial layer, and a fourth epitaxial layer of the first conductivity type provided directly on the third epitaxial layer; a plurality of back-side contacts, which are exposed at a back-side surface of the fourth epitaxial layer, wherein the plurality of back-side contacts comprise: a set of first terminal contacts extending into and electrically contacting the fourth epitaxial layer; a set of second terminal contacts extending into and electrically contacting the second epitaxial layer; a set of first gate contacts extending into the third epitaxial layer; and a set of second gate contacts extending into the first epitaxial layer.
The semiconductor structure of the first aspect can enable the fabrication of the back-side contacts on the back-side of the semiconductor layer without the necessity of performing a front-side implantation. The back-side contacts can be further suitable for coupling to back-side semiconductor devices (e.g., back-side logic devices like CMOS devices, FinFETs, or nanosheet devices like nanosheet FETs), which may be arranged on the back-side of the semiconductor structure to form a new kind of device. Further, the back-side contacts may connect these back-side semiconductor devices to the front-side logic devices.
The semiconductor structure may include more than four epitaxial layers. For instance, the first epitaxial layer to the fourth epitaxial layer may be the rear-most epitaxial layers arranged at the back-side of the semiconductor layer. In addition, for example, a fifth epitaxial layer, or even any further epitaxial layer, may be arranged between the first epitaxial layer and the semiconductor layer. Each of the fifth epitaxial layer or further epitaxial layer may be of the first conductivity type or of the second conductivity type. As described above for the first to fourth epitaxial layers, one or more back-side contacts may also be formed using such a fifth epitaxial layer or further epitaxial layer. For instance, a back-side contact may, respectively, extend into the fifth epitaxial layer or into any further epitaxial layer, and may there contact the epitaxial layer to form a terminal contact, or may be isolated from the epitaxial layer to form a gate contact.
Notably “extending into” in the present disclosure is not necessarily the same as “extending through.” That is, a back-side contact that extends into a respective epitaxial layer does not necessarily extend through that respective epitaxial layer. However, it can end within that respective epitaxial layer. The back-side contact may thereby extend through one or more other epitaxial layers, which are arranged before that respective epitaxial with regard to the extension of the back-side contact. For example, the first gate contacts may extend through the fourth epitaxial layer, the second terminal contacts may extend through the third and the fourth epitaxial layer, and the second gate contacts may extend through the second, the third, and the fourth epitaxial layer.
The first conductivity type may be P-type, and the second conductivity type may be N-type. Alternatively, the first conductivity type may be N-type, and the second conductivity type may be P-type. The respective first or second-conductivity type layers may accordingly be doped with either P-type dopants or N-type dopants. For instance, if the semiconductor layer and/or any epitaxial layer is a silicon layer or a silicon-base layer, the P-type dopants may comprise boron, gallium or indium, and the N-type dopants may comprise phosphorus or arsenic. Other examples are possible, and also other material systems that are known in the art. For instance, instead of silicon, gallium arsenide or gallium nitride may be used as a semiconductor base material, and N-type and P-type dopants can be chosen as known from the art to form N-type and P-type layers.
A “terminal contact” generally is electrically connected to the epitaxial layer it extends into. Thus, it may form an Ohmic contact to that epitaxial layer. As explained below in more detail, a terminal contact may be used to implement a source (terminal) or a drain (terminal), for instance, of a MOS device. However, a first terminal contact may also be used to implement a top contact (terminal) connecting the fourth epitaxial layer, and a second terminal contact may also be used to implement a bulk contact (terminal) connecting to the second epitaxial layer.
In an implementation of the semiconductor structure, the set of second terminal contacts is electrically isolated from the third and the fourth epitaxial layer; the set of first gate contacts is electrically isolated from the third and the fourth epitaxial layer; and the set of second gate contacts is electrically isolated from the first, the second, the third, and the fourth epitaxial layer.
A “gate contact” is typically not electrically connected to the epitaxial layer it extends into. Thus, it may form a MOS contact to that epitaxial layer. As explained below in more detail, a gate contact may be used to implement a gate, for instance of a MOS device or a dummy gate.
For instance, liners may be used for providing the respective isolations to the epitaxial layers, and/or a dielectric material may be used. A first or second gate contact may be isolated from the epitaxial layer it extends into (e.g., by a gate dielectric), while a first or second terminal contact is electrically connected to the epitaxial layer it extends into. Each back-side contact is isolated from the epitaxial layers it extends through.
In an implementation, the semiconductor structure comprises one or more first-conductivity-type Metal-Oxide-Semiconductor (MOS) devices, wherein each first-conductivity-type MOS device is formed by one first gate contact configured as a first gate of the first-conductivity-type MOS device and two first terminal contacts configured as a first source and first drain of the first-conductivity-type MOS device; and/or one or more second-conductivity-type MOS devices, wherein each second-conductivity-type MOS device is formed by one second gate contact configured as a second gate of the second-conductivity type MOS device and two second terminal contacts configured as a second source and second drain of the second-conductivity-type MOS device.
Thus, one or more back-side MOS devices of the first conductivity type, and one or more MOS devices of the second conductivity type are formed, wherein MOS devices may, in particular, be MOS or CMOS field effect transistors (FETs).
In an implementation of the semiconductor structure, at least one first-conductivity-type MOS device comprises a ring-shaped first gate contact surrounding the first drain and a ring-shaped first source surrounding the ring-shaped first gate contact, in a top-view of the semiconductor structure; and/or at least one second-conductivity-type MOS device comprises a ring-shaped second gate contact surrounding the second drain and a ring-shaped second source surrounding the ring-shaped second gate contact, in a top-view of the semiconductor structure.
Thus, a surrounded drain architecture may be formed for any one of the one or more MOS devices defined on the back-side of the semiconductor structure.
In an implementation, the semiconductor structure further comprises one or more isolation structures, each isolation structure extending into the first epitaxial layer and being either an isolation gate formed by one or more second gate contacts or a shallow trench isolation (STI).
The isolation structures may, for instance, separate one or more terminal contacts and/or one or more gate contacts from another, or may separate two or more MOS devices from one another. Notably, in this case the second gate contacts have the function of the isolation gates (and may also referred to as “dummy gates,” in contrast to “active gates” like the first gate or second gate mentioned above). In the implementation form above, the second gate contacts have the function of the second gates for the second-conductivity type MOS devices (e.g., NMOS gates, if the second-conductivity type is N-type).
In an implementation of the semiconductor structure, each first-conductivity-type MOS device further comprises a first bulk contact formed by one second terminal contact and a first top contact formed by one first terminal contact; and/or each second-conductivity-type MOS device further comprises a second bulk contact formed by one second terminal contact and a second top contact formed by one first terminal contact.
In an implementation, the semiconductor structure comprises a first-conductivity-type MOS device and a second-conductivity-type MOS device, which are separated from each other by at least one of the isolation structures.
In an implementation of the semiconductor structure, the back-side surface of the fourth epitaxial layer is divided into one or more first-conductivity type areas and one or more second-conductivity-type areas by a plurality of intersecting isolation structures, wherein each first-conductivity type area comprises one first-conductivity-type MOS device and each second-conductivity-type area comprises one second-conductivity-type MOS device.
For instance, the different areas (may also referred to as “islands”) may be formed and/or separated from each other by a plurality of the isolation structures.
In an implementation of the semiconductor structure, two STIs extend in parallel along a first direction; two isolation gates extend in parallel along a second direction, which is perpendicular to the first direction, and intersect with the two STIs; and a first-conductivity-type area or a second-conductivity-type area is formed within the two STIs and two isolation gates.
In the same way, multiple first- or second-conductivity type areas or islands arranged next to each other (e.g., arranged in rows and/or columns) may be formed on the semiconductor structure back-side.
In an implementation of the semiconductor structure, the fourth epitaxial layer has a higher doping concentration of first conductivity type dopants than the first epitaxial layer; and/or the second epitaxial layer has a higher doping concentration of second conductivity type dopants than the third epitaxial layer.
For instance, the fourth epitaxial layer may be a P+ doped layer, while the first epitaxial layer may be a P− doped layer. The second epitaxial layer may further be an N+ doped layer, while the third epitaxial layer may be an N− doped layer. N-type and P-type can again be reversed. Doping concentrations for P+, P−, N+, and N− may respectively be 1019 to 1021 cm−3 for N+ and P+, and 1016 to 1019 cm−3 for N− and P−.
In an implementation of the semiconductor structure, the one or more front-side logic devices comprise at least one of a Complementary MOS (CMOS) device (e.g., a FinFET device) and a nanosheet device.
In an implementation of the semiconductor structure, a first gate contact and/or a second gate contact has a triangular tip or a round tip formed, respectively, within the third epitaxial layer and/or the first epitaxial layer.
Thus, different gate shapes can be realized.
In an implementation of the semiconductor structure, each of the at least four epitaxial layers is a silicon layer.
A second aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising: forming a semiconductor layer and at least four epitaxial layers on a back-side of the semiconductor layer; forming one or more front-side logic devices, which are at least partly arranged in a front-side of the semiconductor layer; wherein the four epitaxial layers comprise a first epitaxial layer of a first conductivity type, a second epitaxial layer of a second conductivity type provided directly on the first epitaxial layer, a third epitaxial layer of the second conductivity type provided directly on the second epitaxial layer, and a fourth epitaxial layer of the first conductivity type provided directly on the third epitaxial layer; forming a plurality of back-side contacts, which are exposed at a back-side surface of the fourth epitaxial layer, the plurality of back-side contacts comprising a set of first terminal contacts extending into and electrically contacting the fourth epitaxial layer; a set of second terminal contacts extending into and electrically contacting the second epitaxial layer; a set of first gate contacts extending into the third epitaxial layer; and a set of second gate contacts extending into the first epitaxial layer.
In an implementation of the method, forming the semiconductor layer and the at least four epitaxial layers on a back-side of the semiconductor layer comprises: providing a semiconductor substrate; forming an etch stop layer on the semiconductor substrate; forming the four epitaxial layers, starting with the fourth epitaxial layer, on the etch stop layer; forming the semiconductor layer on the first epitaxial layer; thinning the semiconductor substrate to the etch stop layer; and removing the etch stop layer.
This describes an implementation with a dedicated etch stop layer. The etch stop layer may be a silicon germanium layer, in particular, if the semiconductor layer is a silicon or silicon-based layer. For instance, the etch stop layer may have a thickness in a range of 10-100 nm, in particular, 40-60 nm.
In an implementation of the method, forming the semiconductor layer and the at least four epitaxial layers on a back-side of the semiconductor layer comprises: providing a semiconductor substrate; forming the four epitaxial layers, starting with the fourth epitaxial layer, on the semiconductor substrate; forming the semiconductor layer on the first epitaxial layer; and thinning the semiconductor substrate to the fourth epitaxial layer, which serves as an etch stop layer.
This describes an implementation, in which the fourth epitaxial layer is also an etch stop layer. For instance, the fourth epitaxial layer may be a silicon germanium layer, in particular, if the semiconductor layer is a silicon layer or silicon-based layer.
In an implementation of the method, each of the at least four epitaxial layers is a silicon layer or silicon-based layer; and/or the etch stop layer, which is formed on the semiconductor substrate, is a silicon germanium layer.
The method of the second aspect can achieve the same potential advantages as the semiconductor structure of the first aspect, and may be extended by respective implementations as described above for the semiconductor structure of the first aspect.
A third aspect of this disclosure provides a device comprising a semiconductor structure according to the first aspect or any of its implementations; and one or more back-side semiconductor devices, which are coupled to the plurality of exposed back-side contacts of the semiconductor structure.
For instance, the back-side semiconductor devices may comprise back-side logic devices (e.g., CMOS devices, FETs, FinFETs, nanosheet devices, or the like). For example, the back-side semiconductor devices may be part of a PDN for the one or more front-side logic devices.
In summary of the above-described aspects and implementations thereof, objectives of the present disclosure are achieved by the at least four stacked epitaxial layers. These epitaxial layers may be in-situ doped epitaxial layers, and may be doped as follows (from the fourth epitaxial layer to the first epitaxial layer): P+; N−; N+; P− for a P-type semiconductor layer, or N+; P−; P+; N− (i.e., reversed doping types) for an N-type semiconductor layer.
The at least four epitaxial layers can be used to fabricate the back-side contacts, and further to build the first-conductivity or second-conductivity type areas, for example, through a network of intersecting trenches that are used to define the various active gates and dummy gates, and/or STIs, and/or the contacts, at different (epitaxial layer) depths.
As an example, as back-side devices in the semiconductor structure, an NMOS source and/or NMOS drain may be formed by second terminal contacts reaching the second epitaxial (N+) layer, while a PMOS source and/or PMOS drain may be formed by first terminal contacts reaching the fourth epitaxial (P+) layer. STIs and NMOS gates may further reach the first epitaxial (P−) layer, while PMOS gates may reach the third epitaxial (N−) layer. Notably, there may be additional gate or terminal contacts in each area, as will be described further below.
The above, as well as additional, features will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.
All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.
Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout.
Notably, “back-side” and “front-side” are used as terms relative to each other in this disclosure. Typically, any structures and devices at the front-side are those that are processed first in a semiconductor fabrication process, while any structures and devices at the back-side are those that are processed after the front-side structures and devices, particularly, late in the semiconductor fabrication process.
In particular, the semiconductor structure 20 of
The one or more front-side logic devices 22 are at least partly arranged in a front-side of the semiconductor layer 21. As shown in
Further, the semiconductor structure 20 comprises at least four epitaxial layers 23 (e.g., 23a, 23b, 23c, and 23d) (it may particularly comprise more than four epitaxial layers 23, e.g., five, six or even more such epitaxial layers 23), which are arranged on a back-side of the semiconductor layer 21. These four or more epitaxial layers 23 may be formed in-situ and/or epitaxially. Further, these epitaxial layers 23 may form an epitaxial layer stack, which is arranged on the semiconductor layer 21.
The at least four epitaxial layers 23 comprise a first epitaxial layer 23a of a first conductivity type, a second epitaxial layer 23b of a second conductivity type provided directly on the first epitaxial layer 23a, a third epitaxial layer 23c of the second conductivity type provided directly on the second epitaxial layer 23b, and a fourth epitaxial layer 23d of the first conductivity type provided directly on the third epitaxial layer 23c.
The plurality of back-side contacts 24 are furthermore exposed at a back-side surface of the fourth epitaxial layer 23d, i.e., they are accessible via the back-side surface, and may be formed in the epitaxial layer stack of the four or more epitaxial layers 23. Thereby, different back-side contacts 24 may extend into different epitaxial layers 23 of the stack (while being isolated from epitaxial layers 23, through which they extend). That means, different back-side contacts 24 may be processed into different depths of the epitaxial layer stack.
The plurality of back-side contacts 24 comprises different types of back-side contacts 24. In particular, the plurality of back-side contacts 24 comprises a set of first terminal contacts 24a, wherein each first terminal contact 24a extends into and electrically contacts the fourth epitaxial layer 23d. Further, the plurality of back-side contacts 24 comprises a set of second terminal contacts 24b, wherein each second terminal contact 24b extends into and electrically contacts the second epitaxial layer 23b. The set of the second terminal contacts 24b may thereby extend through and may be electrically isolated from, respectively, the third epitaxial layer 23c and the fourth epitaxial layer 23d. Notably, a set of terminal contacts 24a or 24b may respectively comprise one or more of the terminal contacts 24a or 24b.
Further, the plurality of back-side devices 24 comprises a set of first gate contacts 24c, where each first gate contact 24c extends into the third epitaxial layer 23c. The set of the first gate contacts 24c may extend through the fourth epitaxial layer 23d, and may be electrically isolated from the third epitaxial layer 23c and the fourth epitaxial layer 23d, respectively. Further, the plurality of back-side devices 24 comprises a set of second gate contacts 24d, wherein each second gate contact 24d extends into the first epitaxial layer 23a. The set of second gate contacts 24d may extend through the second epitaxial layer 23b, the third epitaxial layer 23c, and the fourth epitaxial layer 23d. Further, the set of second gate contacts 24d may be electrically isolated from the first, the second, the third, and the fourth epitaxial layers 23a, 23b, 23c, 23d. Notably, a set of gate contacts 24c or 24d may respectively comprise one or more of the gate contacts 24c or 24d.
For instance, as an example of the semiconductor structure 20 of
Notably, there is no requirement that the number of epitaxial layers 23 is a multiple of four. That is, e.g. according to the above layer (doping) sequences, also five, six, or seven epitaxial layers 23 are possible, wherein in this case four layers of the five or more epitaxial layers 23 are the first epitaxial layer 23a to fourth epitaxial layer 23d (e.g., P−, N+, N−, P+).
Moreover, in any implementation of the at least four epitaxial layers 23, it is also possible that any of the first epitaxial layer 23a to the fourth epitaxial layer 23d has a non-constant or graded doping profile. For example, in this case the doping concentrations for any epitaxial P+, P−, N+, or N− layer may respectively vary within 1019 to 1021 cm−3 for N+ and P+ layers (for example, in a graded manner), and within 1016 to 1019 cm−3 for N− and P− layers (for example, in a graded manner).
Further, in any implementation of the at least four epitaxial layers, it is also possible that any of the first epitaxial layer 23a to the fourth epitaxial layer 23d comprises a first sublayer having a higher doping concentration and a second sublayer having a lower doping concentration than the first sublayer, wherein the first sublayer is arranged directly on top of the second sublayer, or vice versa. For instance, the second epitaxial layer 23b may comprise a first N− sublayer and a second N+ sublayer, i.e., it may be referred to as an N−/N+ layer. In this example, the at least four epitaxial layers 23 may form a doping/layer sequence of P−, N−/N+, N−, P+ (from first epitaxial layer 23a to fourth epitaxial layer 23d). With reversed conductivity types, the layer sequence in this example would be N−, P−/P+, P−, N+ (from first epitaxial layer 23a to fourth epitaxial layer 23d). The N-/N+ or P−/P+ layer may reduce a hot carrier effect, band-to-band tunneling, and a parasitic capacitance. The first sublayer and the second sublayer of any epitaxial layer 23 may have different thicknesses. For example, the first sublayer may be thinner than the second sublayer. In the above example of the second epitaxial layer 23b being an N−/N+ (or P−/P+) layer, the first N− (or P−) sublayer may have a thickness of 3-6 nm, while the second N+ (or P+) sublayer has a thickness of 10 nm or larger.
Moreover, each epitaxial P+ layer or P−/P+ layer of the at least four epitaxial layers 23 may define a PMOS level, and each epitaxial N+ layer or N−/N+ layer of the at least for epitaxial layers 23 may define an NMOS level. It is also possible to have a different Vth level (threshold voltage) through a different channel doping in each vertical level of the epitaxial layers 23.
The epitaxial layer stack, in particular, the fourth epitaxial layer 23d, may be exposed at the back-side of the semiconductor structure 20. This may, for instance, be achieved by performing substrate thinning as explained further below. Thus, the back-side contacts 24 may be formed in the four epitaxial layers 23, and may be exposed at the back-side surface of the fourth epitaxial layer 23d.
Each back-side contact 24 may be provided with one of several different functions. For example, one or more PMOS devices and/or NMOS devices may be formed by the back-side contacts 24. Each PMOS or NMOS device may thereby comprise a source, a drain, and a gate. However, the back-side contacts 24 may also be used to form isolation gates, e.g., to be arranged between different MOS devices for isolating those MOS devices from each other.
In particular,
In the embodiment of
Each PMOS device in the embodiment of
Furthermore, each PMOS device may further comprise one or more first bulk contacts 37 (“B” in
Moreover, in the embodiment of
In the embodiment of
In
That is, also in the semiconductor structure 20 shown in
Further in
Notably, the semiconductor structure 20 of
The semiconductor structure 20 of
According to the CUT 2 shown in
Notably, in the semiconductor structure 20 shown in the
The method 50 comprises a first step 51 of forming the semiconductor layer 21, for instance, an epitaxial silicon layer or silicon-based layer. Further, the method 50 comprises a second step 52 of forming the at least four epitaxial layers 23 on a back-side of the semiconductor layer 21. In particular, these four epitaxial layers 23 may be realized as shown in
Further, the method 50 comprises a step 54 of forming the plurality of back-side contacts 24, for instance, as shown in the previous
Thereby, the fourth epitaxial layer 23d is formed first and directly in this case on the etch stop layer 61. Then the third epitaxial layer 23c, the second epitaxial layer 23b, and the first epitaxial layer 23a are formed, in this order and one directly on the other, directly on the fourth epitaxial layer 23d. Subsequently, the semiconductor layer 21 may be formed directly on the first epitaxial layer 23a. If there are more than four epitaxial layers, other epitaxial layers may be formed directly on the first epitaxial layer 23a, and the semiconductor layer 21 may then be formed directly on these other epitaxial layers. The at least four epitaxial layers 23 are formed on a back-side of the semiconductor layer 21, and the exposed upper surface of the semiconductor layer 21 represents, accordingly, the front-side surface of the semiconductor layer 21.
The semiconductor structure 20 of
The difference between
In particular,
In particular, the semiconductor structure 20 shown in
While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.
| Number | Date | Country | Kind |
|---|---|---|---|
| 21187116.5 | Jul 2021 | EP | regional |
