Patent Application
20240313101
The present invention generally relates, amongst others, to a semiconductor structure comprising an InAlN barrier layer and to a method of growing thereof. More particularly, it relates to a semiconductor structure comprising an InAlN barrier layer demonstrating improved mobility and sheet resistance and to a method of growing thereof.
GaN-based heterostructures demonstrate high electron velocity and high critical electric field, making them interesting for high-power and high-frequency applications. For example, AlGaN/GaN heterostructures are conventionally used for the manufacturing of field effect transistors also called FETs. In this structure, a two dimensional electron gas, also referred to as 2DEG, is generated by the spontaneous and piezoelectric polarization between AlGaN and GaN.
Increasing the density of the two dimensional electron gas is effective for improving device performance. To increase the density of the two dimensional electron gas, the Aluminium content of the AlGaN barriers should be increased. However, AlGaN with a high Aluminium content is largely strained with respect to GaN. The large strain affects the reliability of devices manufactured from these GaN-based heterostructures.
Ternary InAlN layers have the potential to replace conventional AlGaN as the barrier layer. Ternary InAlN can be lattice matched to GaN for a composition of 17% Indium and 83% Aluminium. A lattice matched InAlN/GaN heterostructure provides a high-density two dimensional electron gas due to the difference in spontaneous polarization at the interface between the InAlN barrier layer and GaN, without any doping. For example, applications in photonics span from the manufacturing of blue and green light-emitting diodes to laser diodes within a broad range of wavelengths. Applications in electronics relate for example to high electron mobility transistors for high-power, high-frequency and/or high temperature devices. Using InAlN as a barrier layer lattice matched to GaN minimizes the effects of misfit-induced defects in Nitride heterostructures devices, giving low strain and low-defect density heteroepitaxial interfaces while providing very high sheet carrier densities. To enhance electron mobility further, an AlN ultrathin layer may be used as a conventional spacer layer between the InAlN barrier layer and the GaN channel layer, thereby forming InAlN/AlN/GaN heterostructures. The electron mobility depends on the abruptness of the interface between GaN and AlN spacer as well as on the quality of the spacer layer itself in terms of compositional uniformity and crystal quality.
Notwithstanding the potential high quality of the manufactured devices, the growth of such structures is not easy to control. Indeed, the growth of InAlN is complicated by the thermal inhibition of the incorporation of Indium into the solid phase at high temperature. In other words, the growth of InAlN films is challenging due to the different optimum growth temperatures of its binary antecedents, InN and AlN: InN dissociates at temperatures above 450° C., whereas AlN must be grown over 1000° C. to obtain good quality crystal films.
Hall measurements performed on the wafer studied on
It is thus an object of embodiments of the present invention to propose a semiconductor structure and a manufacturing method which do not show the inherent shortcomings of the prior art. More specifically, it is an object of embodiments of the present invention to propose a semiconductor structure with improved thermal stability and improved electron mobility and a manufacturing method thereof.
The scope of protection sought for various embodiments of the invention is set out by the independent claims.
The embodiments and features described in this specification that do not fall within the scope of the independent claims, if any, are to be interpreted as examples useful for understanding various embodiments of the invention.
There is a need for a semiconductor structure for high-power and high frequency applications, wherein the semiconductor structure comprises a barrier layer lattice matched to GaN and demonstrates improved thermal stability and improved electron mobility.
This object is achieved, according to a first example aspect of the present disclosure, by a semiconductor structure comprising:
In a prior art semiconductor structure comprising an epitaxial III-N semiconductor layer stack comprising a first active III-N layer, a spacer layer on top of the first active III-N layer and a second active III-N layer comprising Indium Aluminium Nitride on top of the spacer layer, the second active III-N layer comprising Indium Aluminium Nitride is in direct contact with a very tensile strained spacer layer on top of the first active III-N layer. As Indium atoms are larger than the Ga or Al atoms comprised in the first active III-N layer or second active III-N layer, Indium atoms cause a very large local compressive strain in the lattice of the second active III-N layer. During thermal annealing, Indium atoms migrate from the second active III-N layer comprising Indium Aluminium Nitride into at least the spacer layer. In other words, Indium atoms of the second active III-N layer are diffusing or migrating towards the first active III-N layer into at least the spacer layer during thermal annealing, thereby disrupting the compositional uniformity of the spacer layer and smoothening or blurring or softening the interface between spacer layer and first active III-N layer.
The semiconductor structure according to a first example aspect of the present disclosure is suitable for high-power and high-frequency applications. For example, a lattice matched InAlN/GaN heterostructure provides a high-density two dimensional electron gas due to the difference in spontaneous polarization at the interface between the InAlN barrier layer and GaN, without any doping. Using InAlN as a barrier layer lattice matched to the first active III-N layer minimizes the effects of misfit-induced defects in Nitride heterostructures devices, giving low strain and low-defect density heteroepitaxial interfaces while providing very high sheet carrier densities. The spacer layer epitaxially grown between the first active III-N layer and the diffusion barrier layer further enhances the electron mobility of the semiconductor structure.
The diffusion barrier layer epitaxially grown on top of the spacer layer and onto which the second active III-N layer is epitaxially grown prevents the diffusion or the migration of Indium atoms from the second active III-N layer into at least the spacer layer when the semiconductor structure is submitted to high temperatures, such as for example during thermal annealing. Preferably, the diffusion barrier layer prevents the diffusion or the migration of Indium atoms from the second active III-N layer into the spacer layer and the first active III-N layer when the semiconductor structure is submitted to high temperatures, such as for example during thermal annealing. Preferably, the diffusion barrier layer prevents the diffusion or the migration of Indium atoms from the second active III-N layer into the spacer layer and the first active III-N layer and the substrate when the semiconductor structure is submitted to high temperatures, such as for example during thermal annealing.
The diffusion barrier layer thereby guarantees an improved thermal stability, an improved electron mobility and an improved sheet resistance within the semiconductor structure compared to a semiconductor structure comprising an epitaxial III-N semiconductor layer stack without a diffusion barrier layer grown between the spacer layer and the second active III-N layer. In other words, the diffusion barrier layer according to a first example aspect of the present disclosure allows strain mediated diffusion of Indium atoms at least into the spacer layer of the semiconductor structure.
In the context of the present disclosure, with a thickness of the diffusion barrier layer lower than 1 nm, the bottom of the conduction band of the diffusion barrier layer at the interface with the second active III-N layer does not drop below the Fermi level as the conduction band discontinuity is not large and as the charge induced by the spontaneous polarization of the second active III-N layer is not large. For example, the diffusion barrier layer is 1 nm thick or 0.5 nm thick. For example, the diffusion barrier layer is 0.85 nm thick. For example, the diffusion barrier layer comprises a plurality of monolayers of Gallium Nitride. For example, the diffusion barrier layer comprises 4 monolayers or less of Gallium Nitride. Reducing the thickness of the diffusion barrier layer to less than 1 nm minimizes the number of charges within the diffusion barrier layer, thereby minimizing leakage. Reducing the thickness of the diffusion barrier layer to less than 1 nm further brings the 2DEG closer to the second active III-N layer, thereby possibly resulting in an increased alloy scattering. A technical problem solved by the semiconductor structure according to the present disclosure can therefore be to minimize leakage in a semiconductor structure comprising a second active III-N layer comprising Indium Aluminium Nitride.
With the semiconductor structure according to the present disclosure, there are no layers formed between the diffusion barrier layer and the second active III-N layer along a direction of depth of the semiconductor structure. With the diffusion barrier layer according to the present disclosure, it is not necessary to increase a physical separation between the 2DEG and the second active III-N layer.
In the context of the present disclosure, the mole fraction or molar fraction is defined as unit of the amount of a constituent expressed in moles, divided by the total amount of all constituents in a mixture also expressed in moles. According to a first example aspect of the present disclosure, the diffusion barrier layer comprises an Aluminium mole fraction lower than 0.20, such as for example 0.19, 0.18, 0.17, 0.16, 0.15, 0.14, 0.13, 0.12, 0.11, 0.10, etc. In other words, the Aluminium content of the diffusion barrier layer is within the range of 0 to 20%. The content of Aluminium in a layer is defined as the ratio between the number of Aluminium atoms in the layer on the one hand and the total number of all Group III atoms in the layer on the other hand. According to a first example aspect of the present disclosure, the diffusion barrier layer does not comprise Indium.
In the context of the present disclosure, for example, the second active III-N layer is an electron-inducing barrier layer and comprises Indium Aluminium Nitride with an Indium mole fraction for example lower than 0.22. In the context of the present disclosure, for example, the second active III-N layer is an electron-inducing barrier layer and comprises Indium Aluminium Nitride with an Indium mole fraction for example of 0.17 or of 0.18. A second active III-N layer comprising an Indium mole fraction of 0.17 and an Aluminium mole fraction of 0.83 is for example lattice matched to GaN. Preferably, the second active III-N layer is an electron-inducing barrier layer and comprises Indium Aluminium Nitride with an Indium mole fraction for example within the range of 0.14 to 0.22. In an example embodiment, the Indium Aluminium Nitride of the second active III-N layer comprises an Aluminium mole fraction of 0.80 when the Indium Aluminium Nitride comprises an Indium mole fraction of 0.20. In another example embodiment, the Indium Aluminium Nitride of the second active III-N layer comprises an Aluminium mole fraction of 0.86 when the Indium Aluminium Nitride comprises an Indium mole fraction of 0.14. In other words, the Indium Aluminium Nitride of the second active III-N layer for example comprises an Aluminium mole fraction within the range of 0.80 to 0.86. This way, the second active III-N layer is compressive with respect to the first active III-N layer while the first active III-N layer is tensile with an Indium mole fraction of 0.20 or 0.21. Alternatively, the second active III-N layer is an electron-inducing barrier layer and comprises Indium Aluminium Gallium Nitride, with for example a Gallium mole fraction going up to 0.20.
The epitaxial III-N semiconductor layer stack comprises an epitaxial active layer which comprises the first active III-N layer, the spacer layer, the diffusion barrier layer and the second active III-N layer. The epitaxial active layer is formed in-situ by epitaxial growth in a metal-organic chemical vapour deposition epitaxial chamber, also referred to as MOCVD, or in a metal-organic vapour phase epitaxial chamber, also referred to as MOVPE, or in a molecular beam epitaxial chamber, also referred to as MBE, or in a chemical beam epitaxial chamber, also referred to as CBE.
The semiconductor structure can be formed by epitaxial growth by metal-organic chemical vapour deposition (MOCVD) or metal-organic vapour phase epitaxy (MOVPE) or be molecular beam epitaxy (MBE) or chemical beam epitaxy (CBE). In the MOVPE or in the MOCVD process, the epitaxial III-N semiconductor layer stack is epitaxially grown on a substrate, typically at pressures for example comprised between 5 mBar and 1 Bar and typically at temperatures for example comprised between 600° C. and 1200° C. The precursor materials can be but are not limited to ammonia (NH3) for nitrogen; tri-methyl-Ga (TMGa) or tri-ethyl-Ga (TEGa) for Gallium, tri-methyl-Al (TMAl) or tri-ethyl-Al (TEAl) for Aluminium; tri-methyl-Indium (TMIn) for Indium; and Silane (SiH4) or disilane (SiH3)2 for Silicon.
Group III-Nitride refers to semiconductor compounds formed between elements in Group III of the periodic table, for example Boron, also referred to as B, Aluminium, also referred to as Al, Gallium, also referred to as Ga, Indium, also referred to as In, and Nitrogen, also referred to as N. Example of binary Group III-Nitride compounds are GaN, AlN, BN, etc. Group III-Nitride also refers to ternary and quaternary compounds such as for example InAlN, AlGaN, InAlGaN, etc.
A two-dimensional electron gas is a gas of electrons free to move in two dimensions, but tightly confined in the first. This tight confinement leads to quantized energy levels for motion in that direction. The electrons appear to be a 2D sheet embedded in a 3D world. A device of particular interest for high power and/or high frequency applications is the high electron mobility transistor, also referred to as HEMT. According to the present invention, the passivation stack is formed between the epitaxial III-V semiconductor layer stack and the gate. The passivation stack may be formed only under the gate and may serve additionally as gate dielectric. Alternatively, the passivation stack may be formed on top of the epitaxial III-V semiconductor layer stack and may fully cover the epitaxial III-V semiconductor layer stack. Alternatively, the passivation stack may be formed on top of the epitaxial III-V semiconductor layer stack and partially cover the surface of the epitaxial III-V semiconductor layer stack, for example it may be formed in the ungated area between the source and the drain of the high mobility electron transistor according to the present invention, where it serves as passivation and prevents the depletion of the underlying 2DEG.
The diffusion barrier layer comprising GaN in the semiconductor structure according to a first example aspect of the present disclosure demonstrates the largest compressive strain as it lowers the tensile strain component of the spacer layer.
According to example embodiments, the diffusion barrier layer is a monolayer.
This way, the bottom of the conduction band of the diffusion barrier layer at the interface with the second active III-N layer does not drop below the Fermi level as the conduction band discontinuity is not large and as the charge induced by the spontaneous polarization of the second active III-N layer is not large. Additionally, the Aluminium content of the diffusion barrier layer is constant over the monolayer.
According to example embodiments, the first active III-N layer comprises Gallium Nitride.
Preferably, the first active III-N layer is grown epitaxially and comprises pure Gallium Nitride, preferably a monolayer of Gallium Nitride.
Preferably, the spacer layer is grown epitaxially and comprises pure aluminum Nitride.
According to example embodiments, a thickness of the spacer layer is lower than 2 nm.
This way, the spacer layer is kept thin enough to minimize the roughness of the spacer layer. With minimized roughness, the spacer layer prevents the diffusion or the migration of Indium atoms into at least the first active III-N layer. This way, the thermal stability of the semiconductor structure is further improved. In other words, the thinner the spacer layer, the better the thermal stability of the semiconductor structure. Preferably, the thickness of the spacer layer is comprised between 0.5 nm and 1.5 nm. Even more preferably, the thickness of the spacer layer is comprised between 0.8 nm and 1 nm.
The substrate of the semiconductor structure according to a first example aspect of the present disclosure comprises one or more of the following: Si, Silicon-On-Insulator, Silicon Carbide, Sapphire. This way, the manufacturing of the semiconductor structure according to a first example aspect of the present disclosure is compatible with existing manufacturing techniques developed for the complementary metal-oxide-semiconductor technology and processes. In other words, the manufacturing of the semiconductor structure is CMOS-compatible as present features and present process steps can be integrated therein without much additional effort. This reduces the complexity and the costs associated with manufacturing such a semiconductor structure. Preferably, the substrate is a Si substrate, such as a <111> Si substrate, and combinations of thereof, and substrates comprising initial layers, such as a stack of layers. Alternatively, the substrate of the semiconductor structure comprises Germanium, also referred to as Ge, or Ge-On-Insulator, etc. Alternatively, the substrate of the semiconductor structure comprises a free-standing GaN substrate, a free-standing AlN substrate.
Alternatively, the epitaxial III-N semiconductor layer stack comprises an epitaxially grown buffer layer grown between the substrate and the first active III-N layer. The buffer layer may be of a different nature than the substrate, in that for instance the bandgap of the substrate and buffer layer are relatively far apart (such as 1.1 eV and 6.2 eV respectively), in the sense that the buffer layer has a high bandgap, in order to provide present characteristics, such as high break down voltage, e.g. larger than 250 V, preferably larger than 500 V, even more preferably larger than 1000 V, such as larger than 2000 V, or even much larger. The buffer layer is in an example a III-V buffer layer with a high bandgap. Therein III refers to Group III elements, now being Group 13 and Group 3 elements, such as B, Al, Ga, In, Tl, Sc, Y and Lanthanide and Actinide series. Therein V refers to Group V elements, now being N Group elements, such as N, P, As, Sb, Bi. The buffer layer comprises a stack of layers, in an example typically the first one being a nucleation layer.
Alternatively, the semiconductor structure further comprises a Silicon base wafer, the buffer layer stack being separated from the Silicon base wafer by means of an AlN nucleation layer which is in direct contact with the Silicon base wafer and the buffer layer. Alternatively, a total thickness of the nucleation layer is within the range between 10 nm and 200 nm. According to preferred embodiments, the buffer layer stack has an upper buffer layer and a lower buffer layer, the lower buffer layer being in direct contact with the AlN nucleation layer and the upper buffer layer being in direct contact with the active layer. According to preferred embodiments, a total thickness of the buffer layer stack is within the range between 500 nm and 10 μm. The layers of the buffer layer stack are preferably all (In)AlGaN layers.
According to example embodiments, the semiconductor structure further comprises a passivation layer on top of the second active III-N layer.
The passivation layer is formed in-situ with the formation of the epitaxial III-N semiconductor layer stack. This way, a fully crystalline passivation layer is epitaxially grown on top of the epitaxial III-N semiconductor layer stack. Alternatively, a partially crystalline passivation layer is epitaxially grown on top of the epitaxial III-N semiconductor layer stack. The passivation layer may also be formed by ex-situ deposition with the help of epitaxy tools like atomic layer deposition, also referred to as ALD, chemical vapor deposition, also referred to as CVD, or physical vapor deposition, also referred to as PVD. Alternatively, the passivation layer may be formed by in-situ deposition in a MOCVD or a MBE chamber. Alternatively, the passivation layer may be formed by depositing an amorphous film of the same material and recrystallizing it using thermal anneal. The passivation layer on top of the second active III-N layer for example comprises Gallium Nitride. Alternatively, the passivation layer on top of the second active III-N layer comprises Gallium Nitride and Silicon Nitride.
According to example embodiments, the passivation layer comprises Silicon Nitride and/or an oxide layer.
This way, the passivation layer of the semiconductor structure according to a first example aspect of the present disclosure comprises Silicon Nitride and/or an oxide layer which acts as a passivation layer. The oxide layer exhibits an electrically clean interface to the second active III-N layer, a high dielectric constant to maximize electrostatic coupling between electrical contacts formed onto the semiconductor structure and the 2DEG which results in an increase of for example the transconductance of high electron mobility transistors manufactured with the semiconductor structure and a sufficient thickness to avoid dielectric breakdown and leakage by quantum tunneling.
According to example embodiments, there is provided a high electron mobility transistor comprising the semiconductor structure according to a first example aspect of the present disclosure. The high electron mobility transistor comprises:
In the context of the present disclosure, with a thickness of the diffusion barrier layer lower than 1 nm, the bottom of the conduction band of the diffusion barrier layer at the interface with the second active III-N layer does not drop below the Fermi level as the conduction band discontinuity is not large and as the charge induced by the spontaneous polarization of the second active III-N layer is not large. For example, the diffusion barrier layer is 1 nm thick or 0.5 nm thick. For example, the diffusion barrier layer is 0.85 nm thick. For example, the diffusion barrier layer comprises a plurality of monolayers of Gallium Nitride. For example, the diffusion barrier layer comprises 4 monolayers or less of Gallium Nitride. Reducing the thickness of the diffusion barrier layer to less than 1 nm minimizes the number of charges within the diffusion barrier layer, thereby minimizing leakage. Reducing the thickness of the diffusion barrier layer to less than 1 nm further brings the 2DEG closer to the second active III-N layer, thereby possibly resulting in an increased alloy scattering. A technical problem solved by the high electron mobility transistor according to the present disclosure can therefore be to minimize leakage in a high electron mobility transistor comprising a second active III-N layer comprising Indium Aluminium Nitride.
With the high electron mobility transistor according to the present disclosure, there are no layers formed between the diffusion barrier layer and the second active III-N layer along a direction of depth of the semiconductor structure. With the diffusion barrier layer according to the present disclosure, it is not necessary to increase a physical separation between the 2DEG and the second active III-N layer.
A gate electrode is provided in the gate region and a high electron mobility transistor is formed. The gate electrode is in direct contact with the second active III-N layer in the gate region. In other words, no other layer is formed between the gate contact and the second active III-N layer along the direction along the depth of the semiconductor structure. Forming a gate electrode in the gate region comprises a plurality of process steps. For example, this step comprises depositing photoresist and performing a lithography step defining the foot of the gate contact by for example partially removing the passivation layer if present. In this way, some layers of the passivation layer remain below the gate of the high electron mobility transistor and form a gate dielectric to reduce trapping effects and leakage current. The gate electrode is for example a Metal-Oxide-Semiconductor gate, also referred to MOS gate, and can be made by depositing metal stacks, such as for example comprising Ni, Pt, W, WN, or TiN and capped by Al, Au or Cu. Metal patterns are consecutively defined by performing lift-off of the metal on top of the photoresist. Alternatively, the gate metal stack is deposited, for example comprising Ni, Pt, W, WN, or TiN and capped by Al, Au or Cu. Then the photoresist and the lithography steps are performed, and the thus defined photoresist patterns act as a mask for the dry etching of the metal stacks in areas where it is unwanted. Next the photoresist is removed.
According to example embodiments, the second active III-N layer comprises a recess extending partially through the second active III-N layer in the gate region.
Thanks to the recess in the second active III-N layer in the gate region, the gate contact is brought closer to the 2DEG, thereby improving the effect of depletion of electrons from the 2DEG when the gate is biased. With the high electron mobility transistor according to the present disclosure, it is not necessary to remove the second active III-N layer entirely in the gate region, or even to partially remove the diffusion barrier layer in the gate region to form the gate. In other words, the gate contact in the gate region is not in direct contact with the diffusion barrier layer.
According to example embodiments, the high electron mobility transistor further comprises:
For example, an ohmic contact is formed respectively in the source region and/or in the drain region. The source and the drain contacts are ohmic contacts to the 2DEG and can be made by depositing metal stacks, such as for example Ti/Al/Ni/Au, Ti/Al/Mo/Au, Ti/Al/Ti/Au, Ti/Al/Ti/W, Ti/Al/W, Ti/Al/W/Cr, Ta/Al/Ta, V/Al/Ni/Au, etc., in contact with the second active III-N layer. The second active III-N layer may be recessed prior to metal deposition. The contact properties may be further improved by thermal annealing, typically at a temperature comprised between 800° C. and 900° C., such as for example 850° C., in a nitrogen atmosphere or a forming gas atmosphere. Alternatively, additional metal interconnect layers are defined using methods known to a person skilled in the art, to allow low resistivity current pathways for the gate, source and drain currents. If present, the passivation layer is preferably etched away in a source region and a drain region. In other words, the passivation layer is etched away in a source region and in a drain region, thereby exposing the second active III-N layer in a source region and a drain region. According to an alternative embodiment, the second active III-N layer is partially etched in a wet etch, for example in an alkaline solution or in resist developer, thereby allowing to form respective ohmic contacts in a source region and in a drain region partly in the second active III-N layer. Once the areas of the ohmic contacts are defined, i.e. when the source region and the drain region have been defined, a metal layer or a stack of metal layers can be deposited, for example by thermal evaporation, or by sputtering, or by e-beam evaporation. Metal patterns are consecutively defined by performing lift-off of the metal, on top of the photoresist and not in contact with the second active III-N layer. Alternatively, the photoresist is first removed and the metal stack comprising for example Ti and Al is deposited and then a second photoresist deposition and photolithography steps are performed to allow dry etching of the metal stack in areas where it is unwanted and removing the photoresist.
According to a second example aspect, there is provided a method for manufacturing a semiconductor structure, wherein the method comprises the steps of:
The method of manufacturing a semiconductor structure according to a second example aspect of the present disclosure is suitable for manufacturing devices for high-power and high-frequency applications. For example, manufacturing a device comprising a lattice matched InAlN/GaN heterostructure provides a high-density two dimensional electron gas due to the difference in spontaneous polarization at the interface between the InAlN barrier layer and GaN, without any doping. Using InAlN as a barrier layer lattice matched to the first active III-N layer minimizes the effects of misfit-induced defects in Nitride heterostructures devices, giving low strain and low-defect density heteroepitaxial interfaces while providing very high sheet carrier densities. The spacer layer epitaxially grown between the first active III-N layer and the diffusion barrier layer further enhances the electron mobility of the semiconductor structure.
The diffusion barrier layer epitaxially grown on top of the spacer layer and onto which the second active III-N layer is epitaxially grown prevents the diffusion or the migration of Indium atoms from the second active III-N layer into at least the spacer layer when the semiconductor structure is submitted to high temperatures, such as for example during thermal annealing. Preferably, the diffusion barrier layer prevents the diffusion or the migration of Indium atoms from the second active III-N layer into the spacer layer and the first active III-N layer when the semiconductor structure is submitted to high temperatures, such as for example during thermal annealing. Preferably, the diffusion barrier layer prevents the diffusion or the migration of Indium atoms from the second active III-N layer into the spacer layer and the first active III-N layer and the substrate when the semiconductor structure is submitted to high temperatures, such as for example during thermal annealing.
The diffusion barrier layer thereby guarantees an improved thermal stability, an improved electron mobility and an improved sheet resistance within the semiconductor structure compared to a semiconductor structure comprising an epitaxial III-N semiconductor layer stack without a diffusion barrier layer grown between the spacer layer and the second active III-N layer. In other words, the diffusion barrier layer according to a first example aspect of the present disclosure allows strain mediated diffusion of Indium atoms at least into the spacer layer of the semiconductor structure.
Preferably, providing a first active III-N layer corresponds to growing a monolayer of pure Gallium Nitride. Preferably, providing a spacer layer on top of the first active III-N layer corresponds to growing a monolayer of pure aluminum Nitride.
According to example embodiments, there is provided a method for manufacturing a high electron mobility transistor, wherein the method comprises the steps of:
According to example embodiments, for providing the diffusion barrier layer on top of the spacer layer a surface temperature is used which is in the range of 725° C. to 825° C.
This way, with the method of manufacturing a semiconductor structure according to a second example aspect of the present disclosure, there is no growth interruption between the growth of the diffusion barrier layer and the growth of the second active III-N layer. In other words, the diffusion barrier layer and the second active III-N layer are both grown under the same processing conditions. The growth of the diffusion barrier layer is performed so that a temperature of the actual growth surface of the diffusion barrier layer being formed on top of the spacer is within the range of 725° C. to 825° C. In other words, a temperature of the surface of the spacer layer before the diffusion barrier layer is grown is in the range of 725° C. to 825° C. and a temperature of the growth surface of the diffusion barrier layer opposite to the surface of the diffusion barrier layer in contact with the spacer layer is in the range of 725° C. to 825° C. during the growth of the diffusion barrier layer on top of the spacer layer. Alternatively, the diffusion barrier layer is grown on top of the spacer layer at a temperature higher than 825° C. In the content of the present disclosure, the spacer layer may be grown at a temperature lower than 800° C. or at a temperature higher than 800° C.
Some example embodiments will now be described with reference to the accompanying drawings.
Although the present invention has been illustrated by reference to specific embodiments, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied with various changes and modifications without departing from the scope thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the scope of the claims are therefore intended to be embraced therein.
It will furthermore be understood by the reader of this patent application that the words “comprising” or “comprise” do not exclude other elements or steps, that the words “a” or “an” do not exclude a plurality, and that a single element, such as a computer system, a processor, or another integrated unit may fulfil the functions of several means recited in the claims. Any reference signs in the claims shall not be construed as limiting the respective claims concerned. The terms “first”, “second”, third”, “a”, “b”, “c”, and the like, when used in the description or in the claims are introduced to distinguish between similar elements or steps and are not necessarily describing a sequential or chronological order. Similarly, the terms “top”, “bottom”, “over”, “under”, and the like are introduced for descriptive purposes and not necessarily to denote relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and embodiments of the invention are capable of operating according to the present invention in other sequences, or in orientations different from the one(s) described or illustrated above.
| Number | Date | Country | Kind |
|---|---|---|---|
| 21184134.1 | Jul 2021 | EP | regional |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2022/068612 | 7/5/2022 | WO |
