Patent Application
20200211903
The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to methods of forming a two-part trench in a semiconductor device that includes one or more field-effect transistors (FETs). The present disclosure also relates to a semiconductor structure with a shaped trench formed by the methods disclosed herein.
In integrated circuit (IC) design, as the number of devices per chip increases, both inter and intra device dimensions decrease. The demand within the semiconductor industry for high density, high performance, and low cost devices and the implementation of nanometer-scale process nodes have resulted in the development of three-dimensional (3D) architectures such as a fin-shaped field effect transistor (FinFET). Within a typical FinFET, the channel between the source and the drain is formed as a raised fin over a substrate. The gate electrode is then formed over the sidewalls and top of the channel.
In some FinFET technologies, a gate cut is performed to interrupt the continuity of a dummy gate in order to divide the dummy gate into segments. The gate cut may produce a trench within the dummy gate and the trench is then filled with a dielectric material. The segmentation is reproduced with the dummy gate being replaced with a replacement metal gate (i.e., the gate electrode).
As fin pitch scales downward, forming the gate cut between the fin and the trench becomes increasingly challenging with respect to process margin limitations. Due to small sizing of this gate cut, conventional gate cut patterning and etching process may cause incomplete removal of the dummy gate material during subsequent replacement metal gate processes, which may reduce yield and cause electrical shorting between adjacent fins. In addition, conventional gate cut processes may also cause incomplete filling by the replacement metal gate material due to small fin-to-trench dimensions, which may result in increased defect occurrence in the device. One possible technique to avoid the drawbacks of decreasing the size of the gate cut is to increase the fin-to-trench dimensions by narrowing the trenches for dielectric material while maintaining the downward scaling of the device. However, the trenches formed by this approach are found to be overly narrow, and gate cut processes to produce such narrow trenches encountered increased process difficulties and required higher process cost.
Therefore, there is a need to provide methods of forming a semiconductor structure that can overcome, or at least ameliorate, one or more of the disadvantages as described above.
In one aspect of the present disclosure, there is provided a method of forming a structure in a semiconductor device by forming a semiconductor layer above a substrate, forming a mask layer above the semiconductor layer, forming a mask opening with sidewalls in the mask layer and exposing the semiconductor layer, depositing a profile control layer on the sidewalls of the mask opening, and forming a trench in the semiconductor layer by simultaneously etching the profile control layer and the exposed semiconductor layer, where the etching of the profile control layer forms the trench with top and bottom sections having different widths.
In another aspect of the present disclosure, there is provided a method of forming a structure in a semiconductor device by forming a dummy gate above a plurality of fins, forming a mask layer above the dummy gate, forming a mask opening with sidewalls in the mask layer and exposing the dummy gate, depositing a profile control layer on the sidewalls of the mask opening, and forming a gate cut trench in the dummy gate by performing a gate cut process simultaneously on the profile control layer and the exposed dummy gate, where the gate cut process includes etching the profile control layer on the sidewalls to form the gate cut trench with top and bottom sections having different widths.
In yet another aspect of the present disclosure, there is provided a semiconductor structure including a semiconductor material disposed above a plurality of fins, a gate cut trench formed in the semiconductor material, the gate cut trench having a top section, a transitional medial section and a bottom section, and the bottom section is narrower than the top section, the transitional medial section is proximally above top edges of the plurality of fins.
The present disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings.
For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the present disclosure. Additionally, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings may be exaggerated relative to other elements to help improve understanding of embodiments of the present disclosure. The same reference numerals in different drawings denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements.
Various illustrative embodiments of the present disclosure are described below. The embodiments disclosed herein are exemplary and not intended to be exhaustive or limiting to the present disclosure.
Referring to
Referring to
As shown in
The substrate 108 may be made of any suitable semiconductor material, such as silicon, germanium, silicon germanium (SiGe), silicon/carbon, other II-VI or III-V semiconductor compounds and the like. The substrate 108 may also include an organic semiconductor or a layered semiconductor, such as Si/SiGe, a silicon-on-insulator or a SiGe-on-insulator. In one embodiment, the substrate 108 includes silicon.
As shown in
As used herein, the term “patterning techniques” includes, but not limited to, wet etch lithographic processes, dry etch lithographic processes or direct patterning processes. Here, the term “processes” includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure.
In another embodiment (not shown), the thickness of the profile control layer 118 deposited on the sidewalls 114 is different from the thickness of the profile control layer 118 deposited on the top surface 116 of the semiconductor layer 102. However, the formed profile control layer 118 on the sidewalls 114 and the top surface 116 are individually uniform, albeit different in their thicknesses. In another embodiment, the preferred thickness of the deposited profile control layer is in the range of about 5 nm to about 25 nm. The thickness of the deposited profile control layer 118 may be determined based on the profile control spacing 122. For example, if a narrower dimension for the profile control spacing 122 is desired, then the amount of material deposited for the profile control layer 118 can be increased such that the profile control layer 118 has a larger thickness.
In one embodiment, the etching process is performed directly after forming the profile control layer 118. The etching process may be performed using suitable etching techniques, such as reactive ion etching (ME), or physical etching (e.g., ion beam induced etching, ion milling). In some embodiments, the etching process includes a gate cut process. The gate cut process may be performed to cut dummy gates in the cross direction to separate FinFET devices.
The etching process recesses the surface 116 of the semiconductor layer 102, while simultaneously etching the remaining profile control layer 118 on the sidewalls of the mask opening. The etching of the semiconductor layer 102 forms an opening 138 in the semiconductor layer 102, and the partial top surface 116a is formed by the opening 138. The profile control spacing 122 is maintained during etching of the semiconductor layer 102, i.e., the etching process includes transferring the profile control spacing 122 to have a width for the opening 138 in the semiconductor layer 102 that is substantially the same, as shown in
Although not shown in
As described herein, the etching of the profile control layer 118 and the semiconductor layer 102 is simultaneous, however, the etch selectivity of the profile control layer 118 and the semiconductor layer 102 may be the same or different. In some embodiments, the semiconductor layer 102 has a higher or equal etch selectivity with respect to the profile control layer 118 depending on the selection of materials, respectively. The profile control layer 118 controls the profile of the formed trench (e.g., the relative depth and width of the top and bottom sections), in accordance with the present disclosure.
In one embodiment, the profile control layer 118 includes the same material as the semiconductor layer 102. For example, if the semiconductor layer 102 and the profile control layer 118 are both made of amorphous silicon, then the etch rates of the dummy and profile control layers (102 and 118, respectively) are the same, and the subsequently formed trench has top and bottom sections with substantially equal depth. In another embodiment, the profile control layer 118 is a different material from the semiconductor layer 102, such as an oxide containing compound, a nitride containing compound, and a metal oxide compound (e.g., titanium oxide, aluminum oxide, etc.). For example, if the semiconductor layer 102 is amorphous silicon and the profile control layer 118 is aluminum oxide, then the etching is more selective to the semiconductor layer 102 than the profile control layer 118, and the etch rate of the semiconductor layer 102 is faster than the etch rate of the profile control layer 118, thereby forming a trench with the bottom section having a larger depth than the top section.
Referring to
Advantageously, by forming a gate cut trench with the bottom section being narrower than the top section, it is found to increase the process margin limitations for forming a gate cut structure by increasing fin-to-trench dimensions, while addressing the downscaling requirements of semiconductor devices. More advantageously, the increased fin-to-trench dimension is found to enable complete pull of the dummy gate in subsequent replacement metal gate processes. Also advantageously, the increased fin-to-trench dimension may enable complete filling of replacement metal gate material, thereby avoiding defects in the device.
As described herein, the bottom section 128 is narrower than the top section 124. The mask opening functions to define the width 130 of the top section 124, as shown in
Advantageously, the profile control spacing 122 will control and define the width of the bottom section 128. In particular, the dimension of the profile control spacing 122 will be transferred to the width of the bottom section 128 of the formed trench 202. For example, the presence of the profile control spacing 122 during the etching process enables the width of the bottom section 128 to be narrower than the width of the top section 124. The depth of the bottom section 128 of the trench 202 may be defined by a pre-determined thickness of the mask layer 110. For example, if both the profile control layer and the semiconductor layer include the same material, then the resulting etched depth of the bottom section 128 is substantially the same as the thickness of the mask layer 110.
Referring to
It shall be noted that embodiments of the methods disclosed in the present disclosure may be applicable in other semiconductor processing technologies or semiconductor fabrication stages (e.g., front end of line or back end of line processes). In particular, the disclosed method of forming a trench may be applicable for forming a via opening in a semiconductor device, forming an isolation structure in a semiconductor device, or the like.
Throughout this disclosure, the terms top, upper, upwards, over, and above refer to the direction away from the substrate. Likewise, the terms bottom, lower, downwards, under, and below refer to the direction towards the plurality of fins. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Similarly, if a method is described herein as involving a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise”, “include”, “have”, and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or device. Occurrences of the phrase “in one embodiment” herein do not necessarily all refer to the same embodiment.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. Furthermore, there is no intention to be bound by any theory presented in the preceding background or the following detailed description.
Additionally, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. In particular, various processes in the manufacture of integrated circuits are well-known and so, in the interest of brevity, many conventional processes are only mentioned briefly herein or omitted entirely without providing the well-known process details.
As will be readily apparent to those skilled in the art upon a complete reading of the present application, the methods of forming the semiconductor structure disclosed herein may be employed in replacement metal gate processes for forming FinFET components on a semiconductor device, and may be employed in manufacturing a variety of different integrated circuit products, including, but not limited to, logic products, memory products, complementary metal oxide semiconductor (CMOS) devices, etc.
