The invention relates in general to a semiconductor substrate with reduced threading dislocation density. More particularly, the semiconductor substrate is formed of nitrides of group III metals with wurtzite crystal structure and grown in vapor phase either on a (0001) oriented foreign substrate, lattice mismatched to the semiconductor substrate materials, or on existing (0001) oriented highly dislocated layer formed of the semiconductor substrate materials. The invention also relates to a device utilizing and a method of manufacturing such substrate.
Growth of (0001) oriented nitrides of group III metals with wurtzite crystal structure on a foreign substrate with large lattice mismatch, e.g. sapphire, silicon carbide, silicon, or zinc oxide, occurs via formation of three-dimensional islands on the surface of the substrate. Usually, as the first step, a thin layer is deposited on the substrate at a low temperature. This layer is continuous but possesses a nanosize polycrystalline structure. The layer consists of a mixture of cubic and hexagonal phases. Afterwards, the temperature is raised up to the typical growth temperature and recrystallization of the nucleation layer occurs. During recrystallization, the continuous two-dimensional layer is destroyed and three-dimensional islands of the material in hexagonal phase are formed and grow on the substrate surface as a result of mass transfer through the gas phase. The islands typically have a pyramidal shape. The crystal lattice mismatch at the layer-substrate interface is the reason for the formation of misfit dislocations (MDs) with dislocation lines directed along the interface. These MDs relax elastic strain associated with mismatch and are not harmful for device structures. The island interior at the initial stage of recrystallization is essentially dislocation free and may contain only a small amount of threading dislocations (TDs). The islands demonstrate also twist misorientation of their crystal lattice about the [0001] growth direction. The transition to 2D planar growth mode can be achieved through further growth and coalescence of the islands. Due to misorientation of the islands, TDs of mainly edge type are formed at the boundaries of the merging islands. The density of TDs in real III-nitride films can be as high as 10 cm−2. The vertical TDs propagate through the layer during further growth without reactions and remain in the working zone of electronic and optoelectronic devices. It is known that the presence of such high TD density changes device physical performance. Despite of their high density, TDs are essentially non-equilibrium defects. Therefore their number can be reduced by appropriate material treatment or the choice of growth conditions. During recent years a large amount of experimental researches and practical inventions have been directed to reduce TD densities in III-nitrides.
Method of growth of crystalline epilayers on a lattice mismatched substrate via deposition of thin low temperature layer was disclosed by J. Matthews and W. Stobbs in U.S. Pat. No. 4,174,422. In case of AlxGa1-xN films, it was disclosed by I. Akasaki and N. Sawaki in U.S. Pat. No. 4,855,249. Typical TD density achieved in the epitaxial layers of nitrides of group III metals with wurtzite crystal structure grown on low temperature layers is ˜109 cm−2. Different variations of the method constitute a significant part of the patents devoted to the initiation of nitrides of group III metals growth on a foreign substrate; see e.g. K. Manabe et al in U.S. Pat. No. 5,122,845; S. Nakamura in U.S. Pat. No. 5,290,393; Y. Ohba and A. Hatano in U.S. Pat. No. 5,656,832. It has been also shown by H. Kawai et al in U.S. Pat. No. 5,863,811 that using several low temperature layers can decrease the TD density.
Several other techniques for reduction of dislocation density in crystalline epilayers grown on a lattice mismatched substrate were suggested. T. Mishima et al. in U.S. Pat. No. 5,633,516 suggested using graded lattice constant buffer layers. J. Bean et al. in U.S. Pat. No. 5,091,767 suggested using “dislocation sinks”, amorphous regions of the layer, on the substrate, in which dislocations are annihilated while propagating in the amorphous material. H. Morkoc in U.S. Pat. No. 6,657,232 disclosed a defect filter, comprising islands of one material formed on the underlying material and a continuous layer of a second material over the islands.
The most effective methods found up to now to reduce TD density in epitaxial layers grown on foreign substrates are selective area growth (SEA) and epitaxial lateral overgrowth (ELO) of a layer over a predeposited dielectric mask through openings in it. The first discussion of the principal features of selective epitaxy of semiconductors such as GaAs on Si to our best knowledge was given by D. Morrison and T. Daud in the U.S. Pat. No. 4,522,661. A lot of papers were devoted to SEA and ELO of various conventional III-V semiconductors on highly mismatched substrates. It was reported by D. Kapolnek et al. (Appl. Phys. Lett. 71(9), 1204 (1997)) that there exists high anisotropy in growth of GaN on a sapphire substrate by SEA using linear mask patterns. Vertical and lateral growth rates were reported to have opposite orientation-related minima and maxima, with hexagonal symmetry. The possibility of selective growth of gallium nitride hexagonal microprisms on a (0001) sapphire substrate has been successfully demonstrated by T. Akasaka et al. (Appl. Phys. Lett. 71(15), 2196 (1997)). ELO variations were demonstrated by A. Sakai et al. (Appl. Phys. Lett. 71(16), 2259 (1997)), T. Zheleva et al. (Appl. Phys. Lett. 71(17), 2472 (1997)), and R. Davis et al. in U.S. Pat. No. 6,051,849. It was found by M. Coltrin et al. (MRS Internet J. Nitride Semicond. Res. 4S1, G6.9 (1999)) that ELO feature morphology is influenced also by the mask fill factor. Besides, it was demonstrated by J. Park et al. (Appl. Phys. Lett. 73(3), 333 (1998)) that the vertical growth rate is strongly dependent on both the orientation of mask stripe opening and the fill factor, while the lateral overgrowth is relatively weakly dependent on the fill factor, but depends strongly on the stripe orientation.
In the majority of variations of these techniques, see e.g. U.S. Pat. No. 5,880,485 by D. Marx et al., U.S. Pat. No. 6,252,261 B1 by A. Usui et al., propagation of TDs above the masked regions is blocked by the mask (see
Among in situ techniques, the most efficient one is depositing a dielectric material on the substrate or the bottom epitaxial layer, which produces partial random coverage, i.e. micromasking, of the epilayer surface area by an interlayer of submonolayer thickness (see e.g. U.S. Pat. No. 6,610,144 by U. Mishra and S. Keller). Dielectric material deposited can be e.g. silicon nitride, silicon dioxide or magnesium nitride. It acts as an antisurfactant facilitating three dimensional growth mode in the uncovered substrate regions. The growth of epitaxial film then proceeded via lateral overgrowth of the dielectric covered regions, similar to ELO technique. Part of dislocations either become blocked by the micromask or bended during lateral overgrowth over micromasked regions (see e.g. U.S. Pat. No. 6,802,902 by B. Beaumont at al.) and become parallel to the substrate surface. The efficiency of these techniques is limited by the fact that the mask regions are distributed randomly and do not provide selective treatment of the dislocated regions. The efficiency is also less for the less dislocated layers.
A dislocation reduction technique, which pro vides selective treatment of the dislocations, is disclosed by N. Ledentsov in US Patent Application 20020167022A1. Variations of this technique are also disclosed by R. Croft at al. in patent application WO 2004/008509 A1.
According to the preceding prior art description, despite of all development in the area the known solutions still have plenty of drawbacks and weaknesses. There is an evident need for a substrate formed of nitrides of group III metals having highly reduced dislocation density throughout its surface. Specially, there is a need for an effective, controllable, entirely in situ method of manufacturing such substrates with a surface quality suitable for further epitaxial growth of semiconductor device layers.
The purpose of the invention is to eliminate the above-referred disadvantages of the prior art.
Specifically, the purpose of the invention is to disclose a new type of semiconductor substrate with highly reduced threading dislocation density and surface suitable for epitaxial growth, the substrate being formed of nitrides of group III metals having wurtzite crystal structure and grown in vapor phase either on a (0001) oriented foreign substrate, lattice mismatched to the semiconductor substrate materials, or on existing (0001) oriented highly dislocated layer of the semiconductor substrate materials.
Further, the purpose of the invention is also to disclose a new type of semiconductor device comprising a semiconductor substrate described above.
Finally, the purpose of the invention is also to disclose a new, effective and well controllable in situ method for manufacturing semiconductor substrate of type described above.
The semiconductor substrate in accordance with the invention is characterized by what is presented in claim 1. The substrate is formed of nitrides of group III metals having wurtzite crystal structure and grown in vapor phase either on a (0001) oriented foreign substrate, lattice mismatched to the semiconductor materials, or on existing (0001) oriented highly dislocated layer of the semiconductor substrate materials. Most typical nitrides used are GaN and AlxGa1-xN, 0<x≦1, but also other materials like InyGa1-yN, 0<y≦1, and BN can be used. According to the present invention, the semiconductor substrate comprises a dislocation redirection layer, in which inclination of threading dislocations towards high index crystallographic planes, characterized by indexes other than (0001) and those of the type {1
A semiconductor device in accordance with the present invention is characterized by what is presented in claim 4. The semiconductor device is made of nitrides of group III metals having wurtzite crystal structure and grown in vapor phase either on a (0001) oriented foreign substrate, lattice mismatched to the semiconductor device materials, or on existing (0001) oriented highly dislocated layer of the semiconductor device materials. The device comprises a semiconductor substrate and device layers positioned above said substrate. According to the present invention, the semiconductor substrate comprises a dislocation redirection layer, in which inclination of threading dislocations towards high index crystallographic planes, having indexes other than (0001) and those of the type {1
Said inclination of the threading dislocations in accordance with the present invention can be achieved for example by development of crystallographic plane facets with crystallographic indexes other than (0001) and those of the type {1
Preferably, the dislocation redirection layer according to the present invention has a thickness of 0.2-4 μm in order to assure effective inclination of the threading dislocations. The dislocation reaction layer in accordance with the present invention has preferably a thickness of 1-10 μm to provide sufficient amount of dislocation reactions.
The method of the present invention of manufacturing a semiconductor substrate is characterized by what is presented in claim 7. The physical basis of the developed approach is to force the inclination of initially vertical threading dislocations to enhance probability of dislocation reactions. The semiconductor substrate is made of nitrides of group III metals having wurtzite crystal structure and grown in vapor phase either on a (0001) oriented foreign substrate, lattice mismatched to the semiconductor substrate materials, or on existing (0001) oriented highly dislocated layer of the semiconductor substrate materials. Said nitrides can be e.g GaN, AlxGa1-xN with 0<x≦1, InyGa1-yN with 0<y≦1, and ON. The vapor-phase growth processes can be executed with a vapor-phase epitaxy reactor like metal organic vapor-phase epitaxy or hydride vapor-phase epitaxy. According to the present invention, the method comprises steps of growing a dislocation redirection layer on said foreign substrate or said existing highly dislocated layer, the growing providing intentional inclination of threading dislocations towards high index crystallographic planes, having crystallographic indexes other than (0001) and those of the type {1
The important step for implementing the present method, providing said inclination, for any reactor is providing preferential growth of crystallographic plane facets with crystallographic indexes other than (0001) and those of the type {1
In general, the precipitates are formed during low-temperature deposition of the material with subsequent recrystallization at higher temperature. However, such technique typically results in forming a number of small precipitates with high density tending to merge before reaching the required height. According to the present invention, preferably, but not exclusively, the precipitates are formed during a sequence of short low-temperature depositions, performed in temperature range of 450-700° C., followed by high-temperature layer annealing periods, performed in temperature range of 900-1150° C. Accurate temperatures depend on the materials and reactor type used.
Duration of said short low-temperature depositions can be e.g. some dozens of seconds. During each annealing a part of deposited material is removed from the surface. Process parameters during annealing, such as temperature gradient and annealing time, are chosen to totally remove small precipitates while save large ones. In result, the dominant growth of only the largest precipitates occurs. This results in possibility to obtain precipitates with controlled height and density.
In one preferred embodiment of the method of the present invention the growing of said dislocation redirection layer comprises the steps of 1) formation of said precipitates on the surface of said foreign substrate or said existing highly dislocated layer; and 2) preferential growing of crystallographic plane facets with crystallographic indexes other than (0001) and those of the type {1
In another preferred embodiment of the method of the present invention growing of said dislocation redirection layer comprises the steps of 1) formation of said precipitates on the surface of said foreign substrate or said highly dislocated layer; 2) preferential growing of crystallographic plane facets with crystallographic indexes other than (0001) and those of the type {1
In a third preferred embodiment of the method of the present invention growing of said dislocation redirection layer comprises the steps of 1) formation of the precipitates on the surface of said foreign substrate or said highly dislocated layer; 2) preferential growing of crystallographic plane facets with crystallographic index (0001); 3) in situ selective chemical etching of the regions on the layer surface close to the dislocation cores; 4) in situ deposition of amorphous material into the surface potential minima located in the etch pits; 5) preferential growing of crystallographic plane facets with crystallographic indexes other than (0001) and those of the type {1
Said amorphous material in said preferred embodiments can be e.g. SiN but there are also other alternatives. The process parameters of the in situ deposition are equipment specific and can be different for each individual reactor, so that no generic parameter values can be given.
Said preferred embodiments of the inventive method have clear advantages in comparison with other methods involving deposition of dielectric materials for dislocation masking. The present invention allows in situ deposition of the masking material predominantly to the areas where the dislocation lines are terminated, whereas other methods provide random coverage of the surface. The essential feature of these embodiments of the invention is using the localization of threading dislocations in the surface grooves at intermediate stage of growth.
The thicknesses of the layers of the present invention will now be discussed in more detail. The required thicknesses depend on the targeted threading dislocation density. The thickness of the dislocation redirection layer should provide merging of the precipitates in the continuous film. Preferably it is in the range from 0.2 to 4 μm. This thickness provides large enough areas of the high index facets. Preferably, the thickness of the dislocation redirection layer is 2-3 times more than the precipitate height. The thickness of the dislocation reaction layer is preferably 1-10 μm. According to the approach used in the present invention, reduction of the total dislocation density ρ=ρvρi, which is subdivided into the density ρv of the vertical TDs and the density ρi of the inclined TDs, can be determined from the following system of “reaction-kinetic” equations:
Here h is the layer thickness and it plays a role of evolution variable; the functions in the right hand sides fredirectionv, fredirectioni and freactionv, freactioni describe the processes of vertical dislocations redirection, their transformation into inclined dislocations and the reactions between them, correspondingly. These functions depend on the chosen method for substrate manufacturing and therefore include (in parameterized form) dependence on the growth conditions and masking process. They also explicitly include layer thickness and parameters describing the intensity of dislocation reactions.
For example, the above functions can be chosen as
freactionv=0, and freactioni=κ·ρi2. For such parameterization, p is related to the angle α between the facet planes in the redirection layer and (0001) crystal plane via p=1/γ·cos α/(1−cos α) with γ being the coefficient, which depends on crystal structure and additional factors that strengthen inclination of the vertical dislocations, such as presence of an amorphous material at the crystallite surface, κ is the TD reaction cross-section parameter. Increase of γ (e.g. by deposition of amorphous material) results in faster decrease of density of vertical TDs with thickness. It is important to note that TD density reduction rate depends on the initial TD density. Higher initial TD density leads to faster TD density reduction rate. It results from the fact that at higher TD densities TDs have higher probability to meet and react.
The present invention provides essential advantages compared to the prior art. The substrate according to the invention can have drastically reduced threading dislocation density throughout the surface and is thus well suitable for further epitaxial growth of device layers. The manufacturing method of the invention includes only in situ process steps while many variations of traditional methods necessitate unwanted ex situ processing. The method of the invention is also well controllable in contrast to e.g. micromasking method of the prior art including random mask coverage.
The accompanying figures, which are included to provide a further understanding of the invention and constitute a part of this specification, illustrate embodiments of the invention as well as prior art examples and together with the description help to explain the principles of the invention.
Reference will now be made in detail to the embodiments and examples relating to the present invention, which are illustrated in the accompanying figures.
The semiconductor device 20 of
Prior art solutions illustrated in
In the dislocation redirection layer 4 illustrated in
Flat film 16 of
The manufacturing method illustrated in
Calculated dislocation density in GaN epitaxial layer grown on a foreign substrate and having initial density of TD ρ0=1010 cm−2 is shown as function of the total layer thickness in figure B. The total layer thickness (“layer thickness” in the figure) means the thickness of the whole two-layer structure. The typical value for the dislocation reaction cross-section parameter in GaN was taken equal to 100 nm. Three values of the model representative parameter p were used: (a) p=0.5, (b) p=1, (c) p=2.
The experiments on the layers with initial TD density of about 109 cm−2 showed the reduction of TD density to less than 108 cm−2 after growth of GaN layers of 4 μm total thickness according to the present invention.
It is obvious to a person skilled in the art that with the advancement of technology, the basic idea of the invention may be implemented in various ways. The invention and its embodiments are thus not limited to the examples described above; instead they may vary within the scope of the claims.
Number | Date | Country | Kind |
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FI 20045482 | Dec 2004 | FI | national |
PCT/FI2005/000233 | May 2005 | FI | national |
This application is a divisional filing of U.S. application Ser. No. 11/792,687, filed May 30, 2008, the disclosure of which is incorporated herein by reference.
Number | Date | Country | |
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Parent | 11792687 | May 2008 | US |
Child | 13211627 | US |