Claims
- 1. A method for making a trench DMOS, comprising the steps of:providing an semiconductor device comprising a first region having a first conductivity type and a second region having a second conductivity type, the article having first and second trenches which are in communication with the first and second regions; depositing a first electrically insulating layer over the surface of the first trench, the first insulating layer having a mean thickness over the first trench of t1; and depositing a second electrically insulating layer over the surface of the second trench, said second insulating layer having a mean thickness over the second trench of t2; wherein the ratio t1/t2 is at least about 1.2
- 2. The method of claim 1, wherein t1/t2 is at least about 1.5.
- 3. The method of claim 1, wherein t1/t2 is at least about 2.
- 4. The method of claim 1, wherein t1 is within the range of about 600 to about 840 angstroms.
- 5. The method of claim 1, wherein t1 is within the range of about 750 to about 1050 angstroms.
- 6. The method of claim 1, wherein t1 is within the range of about 1000 to about 1400 angstroms.
- 7. The method of claim 1, wherein the first and second insulating layers are oxide layers.
- 8. The method of claim 7, wherein the first and second insulating layers comprise silicon oxide.
- 9. The method of claim 1, further comprising the step of depositing polycrystalline silicon into the first and second trenches.
- 10. The method of claim 1, wherein the first insulating layer has an essentially uniform thickness over the first trench.
- 11. The method of claim 1, wherein the first region comprises an n doped epitaxial layer, and wherein the second region is a p type diffusion layer.
- 12. The method of claim 11, wherein the semiconductor device further comprises an n+ doped epitaxial layer, wherein the p type diffusion layer is disposed on a first side of the n doped epitaxial layer, and wherein the n+ doped layer is disposed on a second side of the n doped epitaxial layer.
- 13. A trench DMOS device made in accordance with claim 1, said trench DMOS device comprising an active portion and a termination portion, and wherein the first trench is disposed in the termination portion and the second trench is disposed in the active portion.
- 14. A power MOSFET made in accordance with the method of claim 13.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a division of co-pending U.S. patent application Ser. No. 09/595,120, filed Jun. 16, 2000 entitled “Semiconductor Trench Device With Enhanced Gate Oxide Integrity Structure”.
US Referenced Citations (12)
Foreign Referenced Citations (4)
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JP |
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