Patent Application
20190280091
The present invention relates to a semiconductor wafer.
As a technology for growing a group-III nitride semiconductor crystal on a Si wafer, technologies as shown in the following documents, for example, have been considered.
Patent Document 1 has disclosed a group-III nitride epitaxial wafer that is made to suppress cracks occurring during a device forming process. The group-III nitride epitaxial wafer is characterized by including a Si wafer, an initial layer that is in contact with the Si wafer, and a super-lattice stack that is formed on the initial layer and that has a plurality of sets of stacks each having a first layer formed of AlGaN having an Al composition ratio that is larger than 0.5 and is 1 or less, and a second layer formed of AlGaN having an Al composition ratio that is larger than 0 and is 0.5 or less in this order, where the Al composition ratio of the second layer gradually decreases in a direction away from the wafer.
The Patent Document 2 has disclosed a compound semiconductor wafer that can suppress occurrence of cracks, crystal defect or warp of a nitride semiconductor layer, and can improve productivity. The compound semiconductor wafer includes a silicon single crystal wafer having a crystalline plane orientation denoted as the (111) plane, a first buffer layer formed on the silicon single crystal wafer and made of AlxGa1-xN single crystal (0<x≤1), a second buffer layer formed on the first buffer layer and including a plurality of first single layers and a plurality of second single layers that are alternately stacked, each first single layer being made of AlyGa1-yN single crystal (0≤y<0.1) having a thickness of 250 nm or more and 350 nm or less, and each second single layer being made of AlzGa1-zN single crystal (0.9<z≤1) having a thickness of 5.0 nm or more and 20 nm or less, and a semiconductor device forming region formed on the second buffer layer and including at least one or more of nitride-based semiconductor single crystal layers.
Patent Document 3 has disclosed a semiconductor electronic device that can further reduce leak current while suppressing a wafer from warping. The semiconductor electronic device is a semiconductor electronic device that includes a compound semiconductor layer stacked on a wafer with a buffer layer placed therebetween, where the buffer layer has a composite layer in which a second layer is stacked on a first layer, the second layer formed by using a nitride-based compound semiconductor having an Al composition of 0.8 or more, the first layer formed by using a nitride-based compound semiconductor having an Al composition of 0.2 or less.
The Non-Patent Document 1 has described that “it is prospective that if a film can be grown by alternately stacking GaN and AlN such that lattice relaxation is included in AlN on GaN and compressive stress is left in GaN on AlN, the entire film can have the compressive stress by using a strained periodic structure (generally called Strained Layer Super-lattice; hereinafter, referred to as SLS) of GaN/AlN. It is considered that in addition to the SLS, the compressive stress can also be added by using a combination in which an upper stacked film has a larger lattice constant.”
When a group-III nitride semiconductor layer is formed on a Si wafer, the wafer may be warped, and the group-III nitride semiconductor layer may crack due to the difference in thermal expansion coefficient between Si and the group-III nitride semiconductor crystal. To address this issue, as described in the above-mentioned Patent and Non-Patent Documents, a layer in which internal compressive stress is generated (a stress generating layer) is formed in order to balance the generated compressive stress and the tensile stress generated in the nitride crystal layer due to the difference in thermal expansion coefficient. In this way, the semiconductor wafer is prevented from being warped when the room temperature is restored, and the group-III nitride semiconductor layer is prevented from cracking.
However, there are still many things unclear about the control of the warp of a semiconductor wafer by a stress generating layer. Accordingly, it is also important to observe, while making a structure or the physical property of the stress generating layer clear, a relation between the structure or the like and a result of warp experiment. From such a point of view, as a result of experiments and studies for the relation between the structure of the stress generating layer and the warpage, the present inventors achieved the present invention.
The purpose of the present invention is to clarify a relation, when a crystal layer such as a group-III nitride semiconductor is formed by using an epitaxial growth method, between the structure of the buffer layer in which stress is generated and a warpage of the semiconductor wafer, and to provide a semiconductor wafer having a small warpage by specifying the structure of the buffer layer in which the warpage falls within a proper range.
To solve the above-described issue, in a first aspect of the present invention, a semiconductor wafer is provided, the semiconductor wafer including a base wafer, a device forming layer and a buffer layer that is disposed between the base wafer and the device forming layer, the buffer layer having a stacked structure in which first crystal layers formed of AlxGa1-xN and second crystal layers formed of AlyGa1-yN are repeatedly stacked, where an average Al composition AVG (x) of the first crystal layers and an average Al composition AVG (y) of the second crystal layer satisfy the following conditions: 0<AVG (x)≤1, 0≤AVG (y)<1 and AVG (x)>AVG (y), and when TEM observation of a cross-section of the buffer layer is performed at an observation region including one of the first crystal layers, HAADF-STEM intensity I(D) which is a function of a depth D takes a local minimum value Imin at a depth Dmin and takes a local maximum value Imax at a depth Dmax (Dmax>Dmin), and a depth direction distance DD1 from a depth at which the I(D) takes an intermediate value Imid of the Imax and the Imin to a depth at which the I(D) takes the Imin in a monotonous decrease region disposed shallower than the Dmin, and a depth direction distance DD2 from a depth at which the I(D) takes the Imin to a depth at which the I(D) takes the Imax in a monotonous increase region disposed deeper than the Dmin satisfy the following condition: DD1≤0.3×DD2. A second-order differentiation function of the d2I(D)/dD2 of the I(D) may also have zero-crossing points whose number is larger than 1 between the Dmin and the Dmax.
The term “average Al composition AVG (α)” indicates an average value of Al composition ratios over a thickness direction of a crystal layer formed of AlαGa1-αN, and is one of representative values of Al composition ratios in a case where the Al composition ratio changes in the thickness direction.
The term “observation region” indicates a visual field when a Transmission Electron Microscope (TEM) observation is performed on a first crystal layer that has one layer only, and the term “HAADF-STEM intensity I(D)” indicates gradations, that is, changes in electron beam intensity when observing a crystal layer by using a High-angle Annular Dark Field Scanning TEM (HAADF-STEM) method, as a function of a depth D (a distance in a depth direction from any position to the crystal layer. To reduce pulsation caused by an influence of an atom image, an electron beam intensity signal which is directly obtained from a HAADF-STEM image and on which a smoothing process is performed for an appropriate number of times may also be used as the “HAADF-STEM intensity I(D)”. In a HAADF-STEM image, a heavy element looks bright and a light element looks dark, and a contrast in proportion to the square of the atom amount is obtained. For this reason, in a case of the AlxGa1-xN crystal layer, a dark image in proportion to the value of the Al composition x (a low signal intensity) is observed.
The term “Dmin” is a depth indicating that the I(D) takes a local minimum in the observation region, and the term “Imin” indicates the local minimum value of the I(D). The term “Dmax” is a depth indicating that the I(D) takes a local maximum in the observation region, and the term “Imax” indicates the local maximum value of the I(D). The term “Imid” is an intermediate value between the Imin and the Imax, and Imid=(Imax−Imin)/2.
The term “second-order differentiation function d2I(D)/dD2” is a function obtained by further differentiating a first-order differentiation function dI(D)/dD of the I(D). The term “zero-crossing point” indicates a point of the depth D at which the second-order differentiation function d2I(D)/dD2 is 0 between a depth Dmin and a depth Dmax in the observation region.
The thermal expansion coefficient of the device forming layer may also be larger than the thermal expansion coefficient of the base wafer, and the average lattice constant of the second crystal layer may also be larger than the average lattice constant of the first crystal layer. The base wafer may also be a silicon wafer, and the device forming layer may also be a single layer or a stack formed of GaN or AlGaN. Between the base wafer and the buffer layer, a reaction suppressing layer that suppress a reaction between the silicon atom and the group-III atom may also be further included.
Between the reaction suppressing layer and the buffer layer, an intermediate layer in which the lattice constant in the bulk crystal state is larger than the lattice constant of the reaction suppressing layer may also be further included. As an example of the reaction suppressing layer, an AlN layer formed at a low temperature can be given, and as an example of the intermediate layer, an AlGaN layer can be given.
It is preferable that the thickness of the first crystal layer is larger than 5.0 nm and less than 20 nm, the thickness of the second crystal layer is 10 nm or more and 300 nm or less, and the thickness of a nitride crystal layer that is disposed on the base wafer and includes the buffer layer and the device forming layer is 500 nm or more and 13000 nm or less. The AVG (x) and the AVG (y) may also satisfy the following conditions:
0.9≤AVG(x)≤1 and 0≤AVG(y)≤0.3.
The base wafer 102 is a support wafer that supports the reaction suppressing layer 104, the buffer layer 106 and the device forming layer 108. The base wafer 102 is preferably a silicon wafer. By using a silicon wafer as the base wafer 102, material costs can be reduced, and a semiconductor manufacturing apparatus that has been used in a conventional silicon process can be utilized. Accordingly, cost competitiveness can be enhanced. Further, by using a silicon wafer as the base wafer 102, a large wafer whose diameter is 150 mm or more can be industrially utilized at a low price.
When a silicon wafer is used as the base wafer 102, the device forming layer 108 can be made as a single layer or stack formed of GaN or AlGaN. In this case, the meaning of providing the reaction suppressing layer 104 is significant.
The reaction suppressing layer 104 is disposed between the base wafer 102 and the buffer layer 106. The reaction suppressing layer 104 suppresses a reaction between atoms forming the base wafer 102, for example, a silicon atom and a group-III atom. For example, when an upper layer of the reaction suppressing layer 104 is a Group-III nitride semiconductor layer, the reaction suppressing layer 104 can prevent alloying between Ga contained in the group-III nitride semiconductor layer, and atoms (for example, Si) contained in the base wafer 102. As an example of the reaction suppressing layer 104, Alx1Ga1-x1N (0<x≤1) can be given, and as a representative example, an AlN layer can be given. According to the reaction suppressing layer 104, a surface of the base wafer 102 can be protected, and accordingly, the upper layers can be surely supported. Also, the reaction suppressing layer 104 can form an initial nucleus of a crystal layer that is formed on the base wafer 102.
The buffer layer 106 is disposed between the base wafer 102 and the device forming layer 108. The buffer layer 106 includes a stacked structure 106c in which first crystal layers 106a and second crystal layers 106b are repeatedly stacked. The buffer layer 106 functions as a stress generating layer that reduces the warp of the entire semiconductor wafer 100.
The first crystal layer 106a is formed of AlxGa1-xN, and the second crystal layer 106b is formed of AlyGa1-yN. Then, the average Al composition AVG (x) of the first crystal layer 106a and the average Al composition AVG (y) of the second crystal layer 106b satisfy the following conditions: 0<AVG (x)≤1, 0≤AVG (y)<1, and AVG (x)>AVG (y). It is preferable that the AVG (x) and the AVG (y) satisfy the following conditions: 0.9≤AVG (x)≤1 and 0≤AVG (y)≤0.3. The thickness of the first crystal layer 106a can be made to be 1 nm or more and 20 nm or less, and preferably, can be made to be larger than 5.0 nm and less than 20 nm. The thickness of the second crystal layer 106b can be made to be 5 nm or more and 300 nm or less, and preferably, can be made to be 10 nm or more and 300 nm or less.
As an example of the first crystal layer 106a, an AlN layer can be given, and as an example of the second crystal layer 106b, an AlGaN layer can be given. An interface between the first crystal layer 106a and the second crystal layer 106b is not necessarily a clear interface and may also be an interface in which the Al composition ratio continuously changes in the depth direction.
(a) in
The Al composition ratio and the Ga composition ratio of the second crystal layer 106b to which the figure “1” is added are respectively 7.1% and 54.9%, the Al composition ratio and the Ga composition ratio in the upper portion of the first crystal layer 106a to which the figure “2” is added are respectively 55.3% and 5.2%, the Al composition ratio and the Ga composition ratio in the lower portion of the first crystal layer 106a to which the figure “3” is added are respectively 34.3% and 28.0%. Accordingly, it can be learned that the composition of the second crystal layer 106b is close to GaN, the composition of the upper portion of the first crystal layer 106a is close to AlN, and the composition of the lower portion of the first crystal layer 106a is approximately the middle of GaN and AlN. Because an introduction of Ga source material gas is not intentional during the process of forming the first crystal layer 106a, it can be said that a phenomenon that lots of Al atoms are substituted with Ga atoms in the lower portion of the first crystal layer 106a occurs. Note that although reasons of the occurrence of such a substituent phenomenon are unclear, a possibility of a mixture or the like of the residue of Ga atoms within a furnace while forming the first crystal layer 106a is considered as one of the reasons.
Taking these experiment considerations into account, the present inventors analyzed in detail the Al composition (Al/Ga composition ratio) in the depth direction of the first crystal layer 106a by quantifying the gradations of the HAADF-STEM image, found out a correlation between the Al composition and the warpage of the semiconductor wafer, and achieved the present invention.
Note that it is desirable that the second-order differentiation function d2I(D)/dD2 of the I(D) has zero-crossing points whose number is larger than 1 between the Dmin and the Dmax. The zero-crossing point is a point at which the d2I(D)/dD2 intersects the axis of the intensity 0, which is shown by the “black circles” in the drawing. By satisfying the condition, the warpage of the semiconductor wafer 100 can be made small.
The first crystal layer 106a has a large electric resistance because of the average Al composition AVG (x) thereof is large. Also, by repeatedly stacking the stacked structures 106c including the first crystal layer 106a and the second crystal layer 106b, a blocking voltage can be increased. For this reason, the characteristics such as the blocking voltage and mobility of the active layer 112 can be improved while reducing the warp of the semiconductor wafer 100.
The second crystal layer 106b is ideally formed such that the crystal lattices of the second crystal layer 106b are coherently continuous from the crystal lattices of the first crystal layer 106a at the hetero-junction plane between the second crystal layer 106b and the first crystal layer 106a. As described above, the lattice constant in a bulk state of the second crystal layer 106b is larger than the lattice constant in a bulk state of the first crystal layer 106a such that the average Al composition AVG (x) of the first crystal layer 106a and the average Al composition AVG (y) of the second crystal layer 106b satisfy the conditions that 0<AVG (x)≤1, 0≤AVG (y)<1 and AVG (x)>AVG (y). For this reason, compressive stress to the first crystal layer 106a is accumulated in the second crystal layer 106b. Accordingly, the compressive stress is generated in the buffer layer 106. According to the occurrence of the compressive stress in the buffer layer 106, the compressive stress and tensile stress generated in the nitride crystal layer due to a difference in the thermal expansion coefficient are balanced; therefore, the warp of the semiconductor wafer 100 can be reduced.
Also, the buffer layer 106 has a plurality of stacked structures 106c. The plurality of stacked structures 106c may also constitute a super-lattice structure in which a large number of the stacked structures 106c are repeatedly stacked. The number of repeatedly-stacked structures 106c can be made to be 2 to 500, for example. By stacking a large number of the stacked structures 106c, the compressive stress generated in the buffer layer 106 can be made large. Also, the magnitude of the compressive stress generated in the buffer layer 106 can be easily controlled by the number of the stacks of the stacked structures 106c. Further, by stacking a large number of the stacked structures 106c, the improvement of the blocking voltage by the first crystal layer 106a can be further enhanced.
The device forming layer 108 is a crystal layer in which any device such as a transistor or a light emitting diode (LED) can be formed, and for example, when a High Electron Mobility Transistor (HEMT) in which a two-dimensional electron gas (2DEG) is taken as a channel is to be formed, the device forming layer 108 can include an active layer 112 and a Schottky layer 114. As an example of the active layer 112, a GaN layer can be given, and as an example of the Schottky layer 114, an AlGaN layer can be given.
When the thermal expansion coefficient of the device forming layer 108 is larger than the thermal expansion coefficient of the base wafer 102, the average lattice constant of the second crystal layer 106b can be made to be larger than the average lattice constant of the first crystal layer 106a. That is, when the device forming layer 108 is formed by a MOCVD method and the like under a high-temperature environment, as the semiconductor wafer 100 is returned to a room temperature, because thermal contraction of the device forming layer 108 is larger than that of the base wafer 102, the device forming layer 108 receives tensile stress. In such a case, as described above, when the lattice constant in the bulk state of the second crystal layer 106b is set to be larger than the lattice constant in the bulk state of the first crystal layer 106a, the compressive stress is generated in the buffer layer 106 and the tensile stress by the device forming layer 108 can be cancelled.
The active layer 112 is, for example, formed of Alx4Ga1-x4N (0≤x4<1), and is typically a GaN layer. The active layer 112 may also be an AlInGaN layer. The active layer 112 is a layer in which an electron device is to be formed later. The active layer 112 can be divided into two layers, where the upper layer can be a high-purity layer formed of carbon atoms and the like having an impurity concentration that is as small as possible, and the lower layer can be a layer containing carbon atoms. The presence of the carbon atoms in the lower layer can contribute to increase the blocking voltage and the high purity of the upper layer can contribute to reduce the scattering of the carriers caused by the impurity atoms and thus increase the mobility.
The Schottky layer 114 is, for example, an Alx5Ga1-x5N (0<x5<1). Two-dimensional electron gas (2DEG) is generated at the hetero interface between the active layer 112 and the Schottky layer 114, which can function as a channel layer of the transistor.
The Schottky layer 114 can be appropriately modified in accordance with the structure of the transistor to be formed.
The thickness of the nitride crystal layer including the buffer layer 106 and the device forming layer 108 disposed on the base wafer 102 can be made to be 6 nm or more and 20000 nm or less, and preferably, can be 500 nm or more and 13000 nm or less. Since the nitride crystal layer is configured to have a thickness within this range, the warpage of the semiconductor wafer 100 can be reduced. When the thickness of the base wafer 102 is 400 m or more and the diameter of the base wafer 102 is 100 mm or more, the thickness of the reaction suppressing layer 104 is preferably 30 nm or more and 300 nm or less. By making the base wafer 102 and the reaction suppressing layer 104 within the range, the warpage of the semiconductor wafer 100 can be reduced.
The above-described nitride crystal layer has a larger thermal expansion coefficient than the base wafer 102, and as the temperature is decreased from a high temperature at the time of epitaxial growth to the room temperature, the nitride crystal layer is contracted more largely than the base wafer 102, and as a result, the tensile stress is generated in the nitride crystal layer. However, according to the semiconductor wafer 100 of the present embodiment, because the compressive stress by the buffer layer 106 is generated, the compressive stress and the tensile stress by the decrease of the temperature in the nitride crystal layer are balanced, and the warp of the semiconductor wafer 100 can be suppressed.
Note that as long as the stacked structure 106c made of the first crystal layer 106a and the second crystal layer 106b is included in the buffer layer 106, the other layers of the buffer layer 106 can be in an arbitrary configuration. Although an example in which the intermediate layer 110 is formed between the reaction suppressing layer 104 and the buffer layer 106 is described in the above, the intermediate layer 110 may also be formed between the buffer layer 106 and the device forming layer 108, and on an upper layer of the device forming layer 108.
The intermediate layer 110 is a layer which is disposed between the reaction suppressing layer 104 and the buffer layer 106 and is in contact with the reaction suppressing layer 104, and in which the lattice constant in the bulk crystal state is larger than the lattice constant of the reaction suppressing layer 104. The intermediate layer 110 is, for example, formed of Alx2Ga1-x2N (0<x2<1). The intermediate layer 110 can be ideally formed such that the crystal lattices of the intermediate layer 110 are coherently continuous from the crystal lattices of the reaction suppressing layer 104 at the hetero-junction plane between the intermediate layer 110 and the reaction suppressing layer 104. Accordingly, in the intermediate layer 110, the compressive stress is generated due to a difference in the lattice constant from the reaction suppressing layer 104. Also, in the intermediate layer 110, the initial nucleus formed in the reaction suppressing layer 104 is expanded, and a base surface of the buffer layer 106 formed on the upper layer is formed. The thickness of the intermediate layer 110 can be made to be 600 nm or less, for example, 300 nm.
Note that the above describes that the intermediate layer 110 and the reaction suppressing layer 104 are coherently continuous at the hetero interface therebetween, but this requirement is merely ideal. In reality, lattice relaxation occurs due to defects and the like and the coherently grown regions are merely dominant. This has been similarly explained in relation to the hetero interface between the first crystal layer 106a and the second crystal layer 106b.
A plurality of semiconductor wafers 100 (experimental examples 1 to 3 and a comparative example). having different HAADF-STEM intensities I(D) in an observation region were manufactured. That is, as the semiconductor wafers 100 of the experimental examples 1 to 3 and the comparative example, a Si wafer was used for the base wafer 102, and an AlN layer having a designed thickness of 150 to 160 nm and an AlGaN layer having a designed thickness of 250 nm were formed on the (111) plane of the Si wafer as the reaction suppressing layer 104 and the intermediate layer 110. Further, AlN/AlGaN stacked structures (the stacked structures 106c) each made of an AlN layer (the first crystal layer 106a) having a designed thickness of 5 nm and an AlGaN layer (the second crystal layer 106b) having a designed thickness of 28 nm were repeatedly stacked and formed as the buffer layer 106, and a GaN layer (the active layer 112) having a designed thickness of 800 nm and an AlGaN layer (the Schottky layer 114) having a designed thickness of 20 to 50 nm were formed as the device forming layer 108.
A Metal Organic Chemical Vapor Deposition (MOCVD) method was used for forming each of the above-described AlN layer, AlGaN layer and GaN layer. In the MOCVD method, trimethylaluminum (Al(CH3)3) and trimethylgallium (Ga(CH3)3) were used as group-III source material gas, and ammonia (NH3) was used as nitrogen source material gas. The growth temperature is selected within a range from 1100° C. to 1260° C., and a V/III ratio, that is, a flow rate ratio of the group-V source material gas to the group-III source material gas is selected within a range from 160 to 3700. Note that growth time corresponding to the designed thickness is calculated from a growth rate obtained by a preliminary experiment, and the thickness of each layer is controlled by the growth time, and accordingly, the actual thickness and the designed thickness of each layer are different from each other.
To make the depth profile I(D) of the HAADF-STEM intensity in the observation region in the experimental examples 1 to 3 and the comparative example different, the growth condition of the buffer layer 106 (a stack obtained by repeatedly stacking the AlN layers (the first crystal layers 106a) and the AlGaN layers (the second crystal layers 106b) was changed respectively in the experimental examples 1 to 3 and the comparative example.
In the experimental example 1, growth interruption at the time of growth switching between the AlN layer and the AlGaN layer (referred to as “growth interruption” in some cases) was set to “YES”, the V/III ratio of the AlN layer (the first crystal layer 106a) was set to be 1580 and the Al composition of AlGaN layer (the second crystal layer 106b) was set to 0.18. In the experimental example 2, the growth interruption was set to “NO” and the others were set the same as the experimental example 1. In the experimental example 3, the Al composition of the AlGaN layer was set to 0.33, and the others were set the same as the experimental example 1. In the comparative example, the V/III ratio of the AlN layer was set to 260, and the others were set the same as the experimental example 1. Note that the “Al composition” here is a “target value” in the growth condition and is different from the Al composition in an actual crystal layer.
For each semiconductor wafer manufactured in the experimental examples 1 to 3 and the comparative example, the HAADF-STEM intensity I(D) was measured, the first-order differentiation function dI(D)/dD and the second-order differentiation function d2I(D)/dD2 were calculated, and the DD1, the DD2 and the number of zero-crossing points were evaluated. Also, for each semiconductor wafer, the warpage was measured.
As shown in
Corresponding to the difference in the I(D) between the experimental examples 1 to 3 and the comparative example, the DD and the DD2 are different in the experimental examples 1 to 3 and the comparative example. In the experimental examples 1 to 3 in which an absolute value of the warpage falls within 90 μm, DD1/DD2 is 0.2 or less. On the other hand, in the comparative example in which the warpage is as large as 173 μm, DD1/DD2 is as large as 0.3 or more. Also, in the experimental examples 1 to 3 in which the warpage is small, the number of the zero-crossing points is 5. On the other hand, in the comparative example in which the warpage is large, the number of the zero-crossing points is 1.
From the above embodiments, it can be said that it is possible to evaluate the warpage of the wafer by DD1/DD2 or the number of zero-crossing points, and a good warpage can be obtained if DD1/DD2 and the number of zero-crossing points are respectively 0.3 or less (preferably, 0.2 or less) and larger than 1 (preferably, 5 or more).
As described above, by making the DD1 and DD2 defined by the HAADF-STEM intensity I(D) in the observation region of the buffer layer 106 so as to satisfy the condition that DD1≤0.3×DD2 (preferably, DD1≤0.25×DD2, and more preferably, DD1≤0.2×DD2), the warpage of the semiconductor wafer can be made small. Also, by making the number of zero-crossing points defined by the second-order differentiation function d2I(D)/dD2 of the I(D) to be larger than 1 (preferably, 5 or more), the warpage of the semiconductor wafer can be made small.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2016-231901 | Nov 2016 | JP | national |
The contents of the following Japanese patent applications are incorporated herein by reference: NO. 2016-231901 filed in JP on Nov. 30, 2016, andNO. PCT/JP2017/042694 filed on Nov. 28, 2017.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2017/042694 | Nov 2017 | US |
| Child | 16425501 | US |
