Claims
- 1. A method for latching and amplifying a capacitively coupled inter-chip communication signal, comprising:
receiving an input signal on a capacitive receiver pad from a capacitive transmitter pad; feeding the input signal through an inverter to produce an output signal; feeding the output signal through a weakened inverter to produce a feedback signal; and feeding the feedback signal back into an input of the inverter so as to form a latch for the input signal between the inverter and the weakened inverter; wherein the weakened inverter is biased to produce the feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL; wherein VH is slightly higher than a switching threshold of the inverter, and VL is slightly lower than the switching threshold of the inverter, whereby the feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal received on the capacitive receiver pad.
- 2. The method of claim 1, further comprising amplifying an output of the inverter through an amplification stage to produce an amplified output signal.
- 3. The method of claim 2, further comprising establishing the high bias voltage, VH, with a high bias voltage generator and establishing the low bias voltage, VL, with a low bias voltage generator.
- 4. The method of claim 3,
wherein the high bias voltage generator includes a mechanism for adjusting the high bias voltage, VH; and wherein the low bias voltage generator includes a mechanism for adjusting the low bias voltage, VL.
- 5. The method of claim 4, further comprising adjusting the high bias voltage generator and the low bias voltage generator to provide a specified sensitivity to transitions of the input signal.
- 6. The method of claim 4, further comprising adjusting the high bias voltage generator and the low bias voltage generator to provide a specified noise immunity to noise associated with the input signal.
- 7. The method of claim 1, further comprising adjusting an RC time constant for the feedback signal so that the time constant for the feedback signal is significantly larger than the time constant for the transmitted signal from the capacitive transmitter pad, thereby ensuring that the feedback signal does not mask transitions of the transmitted signal.
- 8. An apparatus for latching and amplifying a capacitively coupled inter-chip communication signal, comprising:
a receiving mechanism configured to receive an input signal on a capacitive receiver pad from a capacitive transmitter pad; and a latching mechanism configured to feed the input signal through an inverter to produce an output signal; wherein the latching mechanism is further configured to feed the output signal through a weakened inverter to produce a feedback signal; and wherein the latching mechanism is further configured to feed the feedback signal back into an input of the inverter so as to form a latch for the input signal between the inverter and the weakened inverter; wherein the weakened inverter is biased to produce the feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL; wherein VH is slightly higher than a switching threshold of the inverter, and VL is slightly lower than the switching threshold of the inverter, whereby the feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal received on the capacitive receiver pad.
- 9. The apparatus of claim 8, further comprising an amplifying mechanism configured to amplify an output of the inverter through an amplification stage to produce an amplified output signal.
- 10. The apparatus of claim 9, further comprising a biasing mechanism configured to establishing the high bias voltage, VH, with a high bias voltage generator and establishing the low bias voltage, VL, with a low bias voltage generator.
- 11. The apparatus of claim 10,
wherein the high bias voltage generator includes a mechanism for adjusting the high bias voltage, VH; and wherein the low bias voltage generator includes a mechanism for the low bias voltage, VL.
- 12. The apparatus of claim 11, further comprising an adjusting mechanism configured to adjust the high bias voltage generator and the low bias voltage generator to provide a specified sensitivity to transitions of the input signal.
- 13. The apparatus of claim 11, further comprising an adjusting mechanism configured to adjust the high bias voltage generator and the low bias voltage generator to provide a specified noise immunity to noise associated with the input signal.
- 14. The apparatus of claim 8, further comprising an adjusting mechanism configured to adjust an RC time constant for the feedback signal so that the time constant for the feedback signal is significantly larger than the time constant for the transmitted signal from the capacitive transmitter pad, thereby ensuring that the feedback signal does not mask transitions of the transmitted signal.
- 15. A means for latching and amplifying a capacitively coupled inter-chip communication signal, comprising:
a receiving means for receiving an input signal on a capacitive receiver pad from a capacitive transmitter pad; and a latching means configured to feed the input signal through an inverter to produce an output signal; wherein the latching means is further configured to feed the output signal through a weakened inverter to produce a feedback signal; and wherein the latching means is further configured to feed the feedback signal back into an input of the inverter so as to form a latch for the input signal between the inverter and the weakened inverter; wherein the weakened inverter is biased to produce the feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL; wherein VH is slightly higher than a switching threshold of the inverter, and VL is slightly lower than the switching threshold of the inverter, whereby the feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal received on the capacitive receiver pad.
- 16. The means of claim 15, further comprising an amplifying means for amplifying an output of the inverter through an amplification stage to produce an amplified output signal.
- 17. The means of claim 16, further comprising a biasing means for establishing the high bias voltage, VH, with a high bias voltage generator and for establishing the low bias voltage, VL, with a low bias voltage generator.
- 18. The means of claim 17,
wherein the high bias voltage generator includes a mechanism for adjusting the high bias voltage, VH; and wherein the low bias voltage generator includes a mechanism for the low bias voltage, VL.
- 19. The means of claim 18, further comprising an adjusting means for adjusting the high bias voltage generator and the low bias voltage generator to provide a specified sensitivity to transitions of the input signal.
- 20. The means of claim 18, further comprising an adjusting means for adjusting the high bias voltage generator and the low bias voltage generator to provide a specified noise immunity to noise associated with the input signal.
- 21. The means of claim 15, further comprising an adjusting means for adjusting an RC time constant for the feedback signal so that the time constant for the feedback signal is significantly larger than the time constant for the transmitted signal from the capacitive transmitter pad, thereby ensuring that the feedback signal does not mask transitions of the transmitted signal.
RELATED APPLICATION
[0001] This application hereby claims priority under 35 U.S.C. 119 to U.S. Provisional Patent Application No. 60/460,105, filed on 3 Apr. 2003, entitled “Sense Amplifying Latch with Low Swing Feedback,” by inventors Ivan E. Sutherland, Robert J Bosnyak, and Robert J. Drost (Attorney Docket No. SUN-P9702PSP).
[0002] The subject matter of this application is related to the subject matter in a co-pending non-provisional application by Robert J. Proebsting and Robert J. Bosnyak entitled, “Method and Apparatus for Amplifying Capacitively Coupled Inter-Chip Communication Signals,” having Ser. No. 10/772,106, and filing date 2 Feb. 2004 (Attorney Docket No. SUN-P9031-SPL).
Provisional Applications (1)
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Number |
Date |
Country |
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60460105 |
Apr 2003 |
US |