This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2011-159082, filed on Jul. 20, 2011, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate to a shift register memory and a method of manufacturing the same.
A shift register memory has been proposed to improve the capacity of a memory. The shift register memory does not include a selection element and a data line for each memory element, but transmits data stored in memory elements to the position of a sensor or a data line. Therefore, the shift register memory has the possibility that the memory elements can be arranged with high density and the memory capacity is significantly increased.
In order to utilize this advantage, it is not preferable to provide a control electrode for each bit (each digit) in the shift register memory. Therefore, it is necessary to perform a shift operation with the desired number of digits by adding an action to all length of bit string (shift register).
However, it is not easy to shift all digit data without any error. In particular, in a case of a high-capacity memory, each shift register includes 100 or more digits, and the physical length of the shift register also must be increased. In this case, it is considered that the possibility of an operation error is increased due to the distortion of a signal waveform caused by a capacitance or inductance component.
As described above, in order to achieve a high-capacity shift register memory, a shift register is required to have high reliability such that data of each bit can be transmitted without any error by an operation on all bit string. However, it is considered that such shift operation is difficult for a conventional shift register.
Embodiments will now be explained with reference to the accompanying drawings.
An embodiment described herein is a shift register memory including first and second control electrodes extending in a first direction parallel to a surface of a substrate, and facing each other in a second direction perpendicular to the first direction. The memory further includes a plurality of first floating electrodes provided in a line on a first control electrode side between the first and second control electrodes. The memory further includes a plurality of second floating electrodes provided in a line on a second control electrode side between the first and second control electrodes. Each of the first and second floating electrodes has a planar shape which is mirror-asymmetric with respect to a plane perpendicular to the first direction.
The shift register memory of this embodiment includes one or more shift registers.
The shift register illustrated in
One of the first and second floating electrodes 103A and 103B is used as a memory layer for storing charges and the other floating electrode is used as a buffer layer for transmitting the charges. In this embodiment, for convenience, the first floating electrode 103A is referred to as a memory layer and the second floating electrode 103B is referred to as a buffer layer. In
The shift register illustrated in
The shift register illustrated in
In
Next, the planar shape of each floating electrode 103 will be described.
As illustrated in
Specifically, the floating electrode 103 has a right triangle shape including a first side which is parallel to the X direction, a second side which is parallel to the Y direction, and a third side which is not parallel to the X direction and the Y direction in a plan view. The first side is disposed so as to come into contact with the insulator 102. The second side is disposed closer to the +X direction than the first side.
In
In this embodiment, the first floating electrodes 103A have the same planar shape. However, the first floating electrodes 103A with two or more different shapes may be included. Similarly, the second floating electrodes 103B have the same planar shape. However, the second floating electrodes 103B with two or more different shapes may be included. In addition, the second floating electrode 103B has a planar shape which is mirror-symmetric to the first floating electrode 103A. However, the second floating electrode 103B may have other shapes.
Next, the arrangement of the floating electrodes 103 will be described.
In
Next, the positional relation between the floating electrodes 103, for example, the first floating electrode S2 and the second floating electrodes B2 and B3 will be described.
The floating electrode B3 is adjacent to the side of the floating electrode S2 which faces the +X direction and the floating electrode B2 is adjacent to the side of the floating electrode S2 which faces the −X direction. In
In this embodiment, the distance D1 is set to be shorter than the distance D2 (D1<D2). Preferably, the distance D1 is set to be significantly shorter than the distance D2 (D1<<D2). This structure has the advantage that the charges stored in the floating electrode S2 can be substantially transmitted only to the floating electrode B3 of the floating electrodes B2 and B3, which will be described below. When the length a is set to be longer than the length b, it is easy to achieve arrangement satisfying the condition D1<D2 (furthermore D1<<D2), as compared to when the length a is set to be shorter than the length b.
When the distance D1 is too long, it is difficult to obtain the tunnel effect of charges. When the distance D1 is too short, the tunnel effect of charges is excessive. Therefore, in this embodiment, the distance D1 is set to, for example, 3 nm to 5 nm. In addition, in this embodiment, the distance between the first control electrode 101A and the first floating electrode 103A or the distance between the second control electrode 101B and the second floating electrode 103B is also set to, for example, 3 nm to 5 nm.
In this embodiment, each floating electrode 103 has a right triangle shape in a plan view. However, each floating electrode 103 may have any shape as long as it has a sharp end portion, such as the angular portion β, in the vicinity of the floating electrode 103 which is adjacent thereto in the +X direction. An example of the floating electrode 103 will be described in the following third embodiment.
Next, the operating principle of the shift register memory will be described with reference to
In this state, when the positive voltage is applied to the second control electrode 101B and the negative voltage is applied to the first control electrode 101A, a strong electric field is formed between the angular portion β of each of the first floating electrodes 103A and the second floating electrode 103B which is adjacent thereto in the +X direction. As a result, the electrons in each of the first floating electrodes 103A are emitted (transmitted) to the second floating electrode 103B which is adjacent to the first floating electrode 103A in the +X direction by field emission (
In this embodiment, the electrons in each of the first floating electrodes 103A are substantially emitted only to the second floating electrode 103B which is adjacent to the first floating electrodes 103A in the +X direction, but are not emitted to the second floating electrode 103B which is adjacent to the first floating electrodes 103A in the −X direction. This is because an electric field stronger than that between the first floating electrode 103A and the second floating electrode 103B which is adjacent to the first floating electrode 103A in the −X direction is formed between the first floating electrode 103A and the second floating electrode 103B which is adjacent to the first floating electrodes 103A in the +X direction, according to the condition D1<D2 (preferably, D1<<D2).
Since the overlap area between the first control electrode 101A and the first floating electrodes 103A or the overlap area between the second control electrode 101B and the second floating electrodes 103B is large, capacitive coupling is likely to occur between the electrodes. However, since the smooth surfaces of the electrodes face each other, the electric field can be suppressed such that the concentration of the electric field and electron exchange do not occur between the electrodes. Therefore, in the shift register, the electrons are exchanged between the floating electrodes 103.
Next, in the state illustrated in
As described above, the electrons in the first floating electrodes S1, S2, and S3 are transmitted to the first floating electrodes S2, S3, and S4 which are adjacent to the first floating electrodes S1, S2, and S3 in the +X direction, respectively (
As described above, in this embodiment, a process of respectively applying the positive voltage and the negative voltage to the control electrodes 101A and 101B and a process of respectively applying the negative voltage and the positive voltage to the control electrodes 101A and 101B are alternately performed to transmit charges in each memory layer (103A) to another memory layer which is adjacent to the memory layer in the +X direction. In this embodiment, it is possible to shift stored data using the above-mentioned structure.
In the above description, the voltage is applied to both the first and second control electrodes 101A and 101B. However, no voltage (0 V) may be applied to one of the first and second control electrodes 101A and 101B and a voltage may be applied only to the other control electrode as long as the electric field can be formed between the first and second control electrodes 101A and 101B.
Next, examples of the structure of the memory layer in the first stage of the shift register will be described with reference to
In
In this example, the first control electrode 101A is divided into a control electrode for the memory layer S0 and a control electrode for the other memory layers. In this example, electrons are injected from the control electrode for the memory layer S0 into the memory layer S0. In this way, data is written to the memory layer S0.
In addition, in this example, in order to facilitate the injection of the electrons into the memory layer S0, the following structures can be used. 1) Only the insulator 102 (for example, a silicon oxide film) between the memory layer S0 and the control electrode 101A has a permittivity lower than that of the other insulators 102. 2) The thickness H0 of the insulator 102 between the memory layer S0 and the control electrode 101A is smaller than the thickness H of the other insulators 102.
The voltage applied to the control electrode 101A other than the control electrode 101A for the memory layer S0 is represented by V1 and the voltage applied to the control electrode 101B is represented by V2. In addition, the voltage applied to the control electrode 101A for the memory layer S0 is represented by V0.
In a case in which the structure of 1) or 2) is not used, when electrons are injected into the memory layer S0, the absolute value of the voltage V0 is set to be greater than that of the voltage V1 (|V0|>|V1|). The reason is that the voltage V1 is set to a value at which electrons cannot be injected from the control electrode 101A into the memory layer and the voltage V0 during the injection of electrons needs to be set to a value at which electrons can be injected from the control electrode 101A into the memory layer S0.
In addition, in the case in which the structure of 1) or 2) is not used, when the memory layer S0 is used for transmitting electrons, similarly to the other memory layers, the absolute value of the voltage V0 is set to be equal to or smaller than that of the voltage V1 (|V0|≦|V1|).
When the structure of 1) or 2) is used, a relation other than the above is established between the voltage V0 and the voltage V1.
It is necessary to consider the material or thickness of the insulator 102 between the memory layer S0 and the control electrode 101A for the relation between the voltage V0 and the voltage V1 when electrons are injected into the memory layer S0. Therefore, the relation between the voltage V0 and the voltage V1 varies depending on the design of the shift register.
For example, in the case in which the structure of 2) is used, when the memory layer S0 is used for transmitting electrons, similarly to the other memory layers, the absolute value of the voltage V0 is set to be smaller than that of the voltage V1 (|V0|<|V1|). The reason why |V0|=|V1| is excluded is as follows. When |V0| and |V1| are set to the same value, strong capacitive coupling occurs between the memory layer S0 and the control electrode 101A, according to the relation of the material or thickness of the insulator 102 between the memory layer S0 and the control electrode 101A. As a result, an excessively high voltage is applied to the memory layer S0.
This example differs from the first example in that the control electrode 101A for the memory layer S0 is electrically connected to the memory layer S0.
In this example, the voltage V0 when electrons are injected into the memory layer S0 can be set to an arbitrary value in the range in which no electron is emitted to the buffer layer B1.
In this example, when the memory layer S0 is used for transmitting electrons, similarly to the other memory layers, the absolute value of the voltage V0 is set to be smaller than that of the voltage V1 (|V0|<|V1|). The reason is the same as that in the first example. It is preferable that the voltages V0 and V1 be set such that the voltage applied to the memory layer S0 is equal to the voltage applied to the other memory layers.
The first and second examples of the memory layer S0 in the first stage have been described above. The existing technique may be used as a third structure of a unit for writing data to the memory layer S0. Hereinafter, an example of the structure of a unit for writing data to the memory layer S0 will be described with reference to
In
A reading unit for reading data from the memory layer (or the buffer layer) in the last stage in the shift register can also be implemented by the existing technique. The reading unit can detect the electrons stored in the memory layer in the last stage by providing, for example, a single-electron transistor (SET) illustrated in
Next, a method of manufacturing the shift register memory will be described with reference to
In order to achieve the above-mentioned memory structure, it is necessary to alternately form the floating electrodes 103 which face each other with a gap of several nanometers and have sharp end portions, such as the angular portions β. When the stability of the operation of the memory is considered, it is preferable to accurately set the distance between the control electrodes 101 or the distance between the floating electrodes 103. However, a large variation occurs in the distances in a patterning process using the lithography technique according to the related art.
In the method of this embodiment, first, a semiconductor-on-insulator (SOI) substrate 201 is prepared (
Next, as illustrated in
Next, as illustrated in
In this embodiment, after the silicon nitride film 222 is formed on both side surfaces of the semiconductor layer 213, the silicon nitride film 222 on one side surface is etched by glancing angle ion irradiation. In this way, the structure illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
In this embodiment, the width of the trench is set to be smaller than the pitch between the self-organized films 226 in the X direction and the pitch between the self-organized films 226 which are arranged in zigzag is set to be substantially equal to the pitch between the semiconductor layers 213 in the X direction. The pitches can be set by adjusting the radius of the self-organized films 226, the distance between the sidewall nitride films 225, and the pitch between the semiconductor layers 213 in the X direction.
Next, as illustrated in
Next, the oxide film 221 facing the −X direction in each line pattern is removed by a rare hydrofluoric acid treatment and the side surface of each semiconductor layer 213 which faces the −X direction is exposed (
Next, an epitaxial semiconductor layer is grown on the side surface of each line pattern which faces the −X direction along the crystal plane orientation of the semiconductor layer 213 (
Next, the growth mechanism of the floating electrode 103 will be described with reference to
P1 indicates a growth process of the floating electrode 103 when the sidewall nitride film 225 is absent. When the sidewall nitride film 225 is absent, the epitaxial growth is substantially stopped at the (111) plane on the side surface of the floating electrode 103. As a result, the floating electrode 103 with the shape P1 is formed.
However, when the sidewall nitride film 225 is present, the epitaxial growth is performed on the side surface of the floating electrode 103 facing the sidewall nitride film 225, regardless of the crystal plane orientation. Therefore, the floating electrode 103 with a shape including P1 and P2 is formed.
When the sidewall insulator 225 is a silicon oxide film instead of the silicon nitride film, the epitaxial growth does not occur. Therefore, in this embodiment, a silicon nitride film is used as the sidewall insulator 225.
Hereinafter, the manufacturing method will be continuously described with reference to
Next, as illustrated in
Next, as illustrated in
In this way, the shift register memory is manufactured. According to this method, it is possible to alternately form the floating electrodes 103 each having a sharp end portion, such as the angular portion β. As a result, it is possible to manufacture the shift register having the structure illustrated in
In this embodiment, the shift register having the structure illustrated in
In addition, the method illustrated in
In the method illustrated in
Finally, the effect of the first embodiment will be described.
As described above, in the shift register memory of this embodiment, a plurality of first and second floating electrodes 103A and 103B are arranged between a pair of control electrodes 101 so as to face the first and second control electrodes 101A and 1016, respectively (
In this embodiment, the shift register having the structure illustrated in
As described above, this embodiment can provide a shift register memory with high capacity and reliability and a method of manufacturing the shift register memory with a small number of processes.
In this embodiment, the floating electrodes 103 are silicon layers. However, the floating electrodes 103 may be other semiconductor layers. An example of the semiconductor layers is germanium layers. In this case, the semiconductor layer 213 of the SOI substrate 201 is a germanium layer, not a silicon layer.
In addition, the angular portion α or the angular portion β of each floating electrode 103 may be rounded, as illustrated In
The remaining angular portion (right-angled portion) of the floating electrode 103 may be rounded. In addition, the angle of the angular portion may not be 90 degrees.
Hereinafter, second and third embodiments, which are modifications of the first embodiment, will be described. In the second and third embodiments, the difference from the first embodiment will be mainly described.
A writing device 312 is connected to a floating electrode 103 (floating electrode 103 in the first stage) which is disposed at one end of the shift register 301 and a reading device 311 is connected to a floating electrode 103 (floating electrode 103 in the last stage) which is disposed at the other end of the shift register 301. The former floating electrode 103 is an example of a first end floating electrode, and the latter floating electrode 103 is an example of a second end floating electrode.
The shift register 301 can shift data only in one direction (+X direction), as represented by an arrow E1, but cannot shift data in the reverse direction. Therefore, in the memory illustrated in
Therefore, in order to read necessary data (hereinafter, referred to as “data D”), it is necessary to read all data on the downstream side of the data D, store the read data in a buffer memory once, and read the data D. Then, after the data D is read, data on the downstream side of the data D needs to be written back to the shift register 301. Therefore, a high-capacity buffer memory needs to be provided in a peripheral circuit unit of the memory.
Therefore, this embodiment uses any of the following first to third measures.
In the first measure, as illustrated in
In the first measure, processes are performed in the order of shift, reading, writing-back, shift, reading, writing-back, . . . . In principle, data shift is performed on the writing side and the reading side at the same time. Therefore, in order to store all of the read data in a non-volatile manner, the buffer memory needs to be a non-volatile memory or data in the buffer memory needs to be moved to the non-volatile memory when power is turned off.
In the second measure, as illustrated in
In
In the second measure, the shift register 301A is used for a memory and the shift register 301B is used for a buffer. Therefore, in the second measure, the buffer memory used in the first measure is not needed. In addition, the operation of the shift registers 301A and 301B is the same as a refresh operation for each half cycle. Therefore, it is possible to access data at a high speed and with high reliability.
The shift register 301A has a structure in which the shift register 301B, the interconnect on the upstream side of the shift register 301B, and the interconnect on the downstream side of the shift register 301B replace the interconnect of the shift register 301 illustrated in
In the third measure, the shift register 301 illustrated in
In the third measure, the buffer layer in the first stage and the buffer layer in the last stage are directly connected to each other by the interconnect without passing through the reading device 311 and the writing device 312. Therefore, in the third measure, it is not necessary to write back data in the last stage to the first stage and the data in the last stage becomes data in the first stage. According to the third measure, it is possible to simply treat the read data. In addition, the non-volatility of data is guaranteed when data is transmitted from the buffer layer in the first stage to the memory layer in the next stage.
In the third measure, the shift registers 301A and 301B illustrated in
When the third measure is used, the buffer layer in the first stage may have, for example, the same structure as the memory layer S0 in the first stage illustrated in
Finally, the effect of the second embodiment will be described.
As described above, this embodiment has the structure in which one or more shift registers are connected to each other in an annular shape by the interconnects. Therefore, according to this embodiment, it is possible to reduce the number of buffer memories or it is not necessary to use the buffer memory.
When a plurality of shift registers 301 are arranged on one substrate, the shift registers 301 may be arranged in a direction parallel to the surface (principal surface) of the substrate or they may be stacked in a direction perpendicular to the surface of the substrate such that data is transmitted in the direction perpendicular to the surface of the substrate. In addition, the former arrangement and the latter arrangement may be combined with each other. It is possible to increase the capacity of the memory by increasing the number of shift registers 301 stacked. This arrangement may also be applied when the first to third measures are not used.
Each floating electrode 103 of this embodiment has a planar shape which is mirror-asymmetric with respect to the plane perpendicular to the X direction, similarly to the first embodiment.
However, in this embodiment, each floating electrode 103 includes a plate-shaped electrode portion 401 and a linear electrode portion 402. Reference numerals 401A and 402A indicate a plate-shaped electrode portion and a linear electrode portion of a first floating electrode 103A, respectively, and reference numerals 401B and 402B indicate a plate-shaped electrode portion and a linear electrode portion of a second floating electrode 103B.
The plate-shaped electrode portion 401 has a plate shape which expands in the in-plane direction perpendicular to the Y direction. The plate-shaped electrode portion 401 is, for example, a disk-shaped silicon layer. The first plate-shaped electrode portion 401A is arranged so as to come into contact with an insulator 102A, and the second plate-shaped electrode portion 401B is arranged so as to come into contact with an insulator 102B.
The linear electrode portion 402 has a linear shape which extends from the surface of the plate-shaped electrode portion 401. The first linear electrode portion 402A extends from the surface of the first plate-shaped electrode portion 401A to the second control electrode 101B. The second linear electrode portion 402B extends from the surface of the second plate-shaped electrode portion 401B to the first control electrode 101A. The linear electrode portion 402 is, for example, a whisker, a nanowire, or a nanotube.
Next, the positional relation between the floating electrodes 103, for example, a first floating electrode S2 and second floating electrodes B2 and B3 will be described.
In
In this embodiment, the linear electrode portion 402A of each of the first floating electrodes 103A extends toward the plate-shaped electrode portion 401B of the second floating electrode 103B which is adjacent thereto in the +X direction, and the linear electrode portion 402B of each of the second floating electrodes 103B extends toward the plate-shaped electrode portion 401A of the first floating electrode 103A which is adjacent thereto in the +X direction. Therefore, in this embodiment, the distance D1 is set to be shorter than the distance D2 (D1<D2). It is preferable that the distance D1 be set to be significantly shorter than the distance D2 (D1<<D2). Similarly to the first embodiment, this structure has the advantage that charges in the floating electrode S2 can be substantially transmitted only to the floating electrode B3 of the floating electrodes B2 and B3.
Finally, the effect of the third embodiment will be described.
As described above, in the shift register memory of this embodiment, a plurality of first and second floating electrodes 103A and 103B are arranged between a pair of control electrodes 101 so as to face the first and second control electrodes 101A and 101B, respectively (
In this embodiment, the shift register having the structure illustrated in
As described above, according to this embodiment, it is possible to provide a shift register memory with high capacity and reliability and a method of manufacturing the shift register memory with a small number of processes.
In the second embodiment, the shift register having the structure of the third embodiment may be used instead of the shift register having the structure of the first embodiment.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel memories and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the memories and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
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2011-159082 | Jul 2011 | JP | national |
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6834005 | Parkin | Dec 2004 | B1 |
20110267868 | Fukuzumi et al. | Nov 2011 | A1 |
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Number | Date | Country | |
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20130020627 A1 | Jan 2013 | US |