Patent Application
20190140046
Power devices based on wide-forbidden band (such as silicon carbide (SiC) and gallium nitride (GaN)) are expected to be widely applied in next-generation electric power generation thanks to high breakdown voltage and power density. In SiC power devices, electrical field are often crowded in the junction edge due to discontinuity of junction, resulting in high electric field at the junction edge. The high electric field will cause early breakdown of the junction edge, which greatly limits the device reverse breakdown voltage. Therefore, various junction terminal technologies are often used to mitigate the local electric field crowding effect during design and manufacturing of SiC power devices and to improve device breakdown voltage. Most Commonly used junction terminal technologies include guard ring, junction terminal extension and field plate structure. The guard ring and junction terminal extension requiring no high-quality dielectric materials that are widely applied in the manufacturing of devices. SiC power devices are often based on the N-type SiC substrate and the weak N-type epitaxy layer as the drift region. Correspondingly, the P-type SiC is taken as the junction terminal to form a depletion region for alleviating electrical field at the junction edge.
The inventors of the present disclosure have recognized that, the P-type SiC region can be manufactured by epitaxy growth and ion implantation. Epitaxial growth means to directly grow P-type SiC over the entire surface of the N-type SiC layer. As growth temperature of the P-type SiC is generally high (>1,500° C.), some P-type impurities (such as Al) are inevitably diffused into weak N-type SiC during growth. This results in self-doping over the N-type SiC surface, and even transforms the region into P-type, thus changing the doping characteristics of the N-type SiC surface and influencing the obtaining of low turn-on voltage of power devices. P-type ion implantation for SiC often requires advanced equipment such as high-temperature ion implanter and ultra-high temperature annealing furnace, which restraints the widely adoption by industry due to complex process and high cost.
Various embodiments of the present disclosure provide a SiC power device with a heterojunction terminal and manufacturing method thereof to overcome the technical drawback of the prior art.
Various approaches can be adopted in the present disclosure to solve the technical problems. For example, a SiC power device with a heterojunction terminal comprises from bottom to up a cathode electrode, a substrate layer, an N-type SiC epitaxial layer and an anode electrode, and also comprises a plurality of separated P-type structures, in which, these P-type structures are formed over the N-type SiC epitaxial layer by P-type semiconductor material with growth temperature lower than SiC, which at least are distributed in the anode electrode periphery to form a heterojunction terminal.
In some embodiments, growth temperature the P-type semiconductor material is 600° C.-1,200° C.
In some embodiments, the P-type semiconductor material is P-type GaN or P-type AlGaN.
In some embodiments, the P-type structures comprise a plurality of closed ring structures surrounding the anode electrode periphery, and the closed ring structures are arranged at equidistant or unequal spacing.
In some embodiments, at least part of the anode electrode and the N-type SiC epitaxial layer form Schottky contact.
In some embodiments, the P-type structures also comprise a plurality of separate structures between the anode electrode and the N-type SiC epitaxial layer.
In some embodiments, the P-type structures also comprise a plurality of layered structures between the anode electrode and the N-type SiC epitaxial layer that separate the anode electrode and the N-type SiC epitaxial layer.
In some embodiments, the upper surface of the N-type SiC epitaxial layer is provided with a plurality of grooves, and the P-type structures are formed inside the grooves correspondingly.
In some embodiments, a dielectric layer is provided, wherein, the dielectric layer is arranged over the N-type SiC epitaxial layer and covers the region beyond the anode electrode and the P-type structures in the region.
In some embodiments, the dielectric layer is any one of or a combination of SiNx, SiO2, Al2O3, AlN, wherein, 0<X<1.
A method for manufacturing the SiC power device is provided, comprising:
(1) providing a SiC epitaxial structure, comprising stacked layers of substrate layer and an N-type SiC epitaxial layer;
(2) growing P-type semiconductor material over the N-type SiC epitaxial layer via heteroepitaxial growth, and defining a plurality of separated P-type structures, wherein, the heteroepitaxial growth includes chemical vapor deposition and molecular beam epitaxy, and growth temperature of the P-type semiconductor material is lower than that of SiC; and
(3) manufacturing an anode electrode and a cathode electrode at both sides of the structure in step 2).
In some embodiments, form a plurality of P-type structures via selective epitaxial growth through patterned mask, defined by dry etching or wet etching in step 2).
In some embodiments, deposit a dielectric layer and etch the window opening over the structure obtained in step 2), and manufacture an anode electrode over the window opening in step 3).
In some embodiments, form the anode electrode and the cathode electrode by depositing metals via electron beam deposition, magnetron sputtering, ion evaporation or arc ion evaporation in step 3), and form Schottky contact or ohmic contact via annealing.
Embodiments of the present disclosure can have one or more of the following advantages.
1. A plurality of P-type structures are formed over the N-type SiC epitaxial layer, which are at least distributed in the anode electrode periphery to form a junction terminal structure for alleviating electrical field at the junction edge. These P-type structures are formed by heteroepitaxial of P-type semiconductor materials with growth temperature lower than SiC growth temperature. Due to low growth temperature and different doping mechanism, this effectively prevents from affecting doping characteristics of the N-type SiC epitaxial layer, thus obtaining a high-performance SiC device with high breakdown voltage and low turn-on voltage. In addition, this method greatly reduces requirements for high temperature or complex process and features simple process and low manufacturing costs.
2. The structure is applicable for Schottky barrier diode (SBD), junction barrier Schottky diode (JBS) and PN junction diode. In the latter two structures, the P-type doping region between the anode electrode and the N-type SiC epitaxial layer can also be formed with the junction terminal structure at the same time, which can be widely applied with simple process.
The present disclosure will be explained in details with reference to the accompanying drawings and embodiments. The drawings are only for illustration and better understanding of the present invention. The specific scale can be adjusted based on design requirements. Those skilled in the art should understand that the upper and lower positions as illustrated in the drawings are merely referred to relative positions of the components, which can be flipped to show same components, which should be also fallen into the scope of this specification. In addition, the number of components and structures illustrated in the diagram are only exemplary, which cannot be interpreted as limiting, which can be adjusted based on actual requirements.
With reference to
The P-type structure 150 is directly formed over the N-type SiC epitaxial layer 130 by heteroepitaxial grown of P-type semiconductor material with growth temperature lower than that of the SiC. Specifically, growth temperature of the P-type semiconductor material is 600° C.-1,200° C., and the P-type semiconductor material can be P-type GaN or P-type AlGaN. Taking P-type GaN as an example, growth temperature of P-type GaN is about 700° C., and growth temperature of SiC is usually above 1,500° C. Under such temperature, the P-type doping impurities will not diffuse into the N-type SiC epitaxial layer 130, causing no effects on doping characteristics of the N-type SiC epitaxial layer 130, thus maintaining characteristics and achieving good overall performance of the device. Further, doping concentration of the N-type SiC epitaxial layer 130 is <5×1016/cm3, and doping concentration of the P-type semiconductor material is >5×1017/cm3, and the P-type structure 150 has a depletion region for alleviating electrical field at the junction edge. Compared with P-type SiC (>1×1018/cm3), the P-type semiconductor obtained by heteroepitaxial growth can have same effects with even low doping concentration.
In some embodiments, the P-type structures 150 are a plurality of closed ring structures surrounding the periphery of the anode electrode 140, and the closed ring structures are arranged at equidistant or unequal spacing. The arrangement of the closed ring structures can effectively avoid early breakdown of the device caused by highly concentrated electronic field at the SiC main junction. Under high-voltage blocking status, the depletion region is formed in the main junction and extends outwards. Once horizontal extension of the depletion region along the SiC surface touches the closed ring 150 region, the P-type closed ring will sense a potential. The closed ring potential can effectively help further extension of the depletion region, and avoid electronic field concentration due to narrow depletion region. Further, the sizes of these closed rings, including thickness, width and spacing, are determined based on voltage rating of actual device (such as thickness of 130). For 600-1,200 V voltage-rated devices, thickness of the N-type SiC epitaxial layer 130 is 4-12 μm, and thickness of the corresponding closed ring of the P-type structure 150 is 200-800 nm, and the width can be 0.5-10 μm, and spacing can be 1-10 μm.
The dielectric layer 160 covers the region beyond the anode electrode 140 above the diode structure to alleviate electronic field and effectively increase breakdown voltage. In some embodiments, the medium layer 160 is any one or a combination of SiNx, SiO2, Al2O3, AlN, where, 0<X<1.
In the diode of the embodiment, the substrate is preferred to be a homogeneous SiC substrate, and the anode electrode and the cathode electrode are such metals as Ti, Ni, Pt, Al, Ag, Au, W, Pb and Si as well as their alloys or laminated composites.
The manufacturing method is described below taking the P-type structure of GaN as an example. At first, provide a SiC epitaxial structure, comprising stacked layers of a substrate layer and an N-type SiC epitaxial layer. Grow a P-type GaN layer over the N-type SiC epitaxial layer via chemical vapor deposition method, taking trimethyl gallium (TMGa), trimethylaluminum (TMAl) and ammonia as the Ga source, the Al source and the N source, and the bis(cyclopentadienyl)magnesium (Cp2Mg) as the P-type doping source. Decompose the gas under 700° C. and deposit a P-type GaN layer over the N-type SiC epitaxial layer, and define a plurality of separate P-type structures via dry etching (such as ICP or RIE) of the P-type GaN layer. In this embodiment, the P-type structures are a plurality of closed ring structures; next, deposit a dielectric layer over the surface of the epitaxial structure via chemical vapor deposition, atomic layer deposition, sputtering and etch windows opening through it; deposit metals at the backside of the substrate layer via electron beam deposition, magnetron sputtering, ion evaporation or arc ion evaporation, which is In some embodiments made of Ti/Ni, and anneal the back metal layer for 2 minutes under 1,000° C. to form ohmic contact; finally, deposit metals over the etching windows of the dielectric layer via electron beam deposition, magnetron sputtering, ion evaporation or arc ion evaporation to manufacture an anode electrode, which is preferred to be Ti/Ni, and anneal the anode metal layer for 5 minutes under 550° C. to form Schottky contact. The anode electrode can be thicker than the dielectric layer and covers some parts surrounding the upper surface of the dielectric layer.
In addition, the P-type semiconductor material can also be grown via metal organic vapor phase deposition or molecular beam epitaxy, and the patterning can be realized by selective growth, such as epitaxy through a patterned dielectric mask obtained by photolithography and wet etching.
With reference to
The upper surface of the N-type SiC epitaxial layer 230 is provided with a plurality of grooves 231, and these P-type structures 251 and 252 are formed in the grooves correspondingly. Through contacting the N-type SiC sidewall at a certain groove depth, the PN junction is constructed at the etched SiC surface as well as in the inner side, which effectively reduces reverse leakage current without compromising the forward turn-on voltage. Other structures, such as the cathode electrode 210, the substrate layer 220 and the dielectric layer 160, can be referred to Embodiment 1.
Compared with Embodiment 1, the manufacturing method according to the present embodiment also includes etching the upper surface of the N-type SiC epitaxial layer to form aforesaid grooves before forming the P-type structure. The junction barrier structure and the junction terminal structure are formed at the same time. In some embodiments, the P-type structures 251 are closed ring, and the P-type structures 252 are strip-shaped, which are patterned via etching or selective epitaxy.
With reference to
The aforesaid embodiments are merely used for further description of a SiC power device with a heterojunction terminal and manufacturing method thereof according to the present invention. It should be understood that any simple variations, equivalent changes or modifications will fall within the scope of the disclosures without departing from the substantive features of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201610541460.4 | Jul 2016 | CN | national |
The present application is a continuation of, and claims priority to, PCT/CN2017/090512 filed on Jun. 28, 2017, which claims priority to Chinese Patent Application No. 201610541460.4 filed on Jul. 11, 2016. The disclosures of these applications are hereby incorporated by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2017/090512 | Jun 2017 | US |
| Child | 16236806 | US |
