Patent Grant
10504996
The present disclosure relates to silicon carbide semiconductor devices.
In recent years, silicon carbide has been increasingly employed as a material forming a semiconductor device in order to allow for a higher breakdown voltage, lower loss, the use in a high-temperature environment and the like of the semiconductor device.
A silicon carbide substrate is manufactured with a sublimation-recrystallization method, for example. However, a silicon carbide substrate usually includes dislocations. It is extremely difficult at the present time to manufacture a silicon carbide substrate completely free of dislocations. Japanese Patent Laying-Open No. 2013-34007 (PTD 1) discloses a silicon carbide epitaxial wafer in which step bunching coupled to shallow pits resulting from screw dislocations in a silicon carbide epitaxial layer has a linear density of 5 mm−1.
Makoto Kitabatake and eight others, “Electrical Characteristics Reliability Affected by Defects Analyzed by the Integrated Evaluation Platform for SiC epitaxial films,” Materials Science Forum, 2014, Vols. 778-780, p. 979-984 (NPD 1) discloses a method of evaluating electrical characteristics and reliability affected by defects preset in a silicon carbide epitaxial film.
An object of one embodiment of the present disclosure is to provide a silicon carbide semiconductor device capable of suppressing dielectric breakdown of a gate insulating film.
A silicon carbide semiconductor device according to one embodiment of the present disclosure includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region being in contact with the gate insulating film at the first main surface and having a first conductivity type, a second body region being in contact with the gate insulating film at the first main surface and having the first conductivity type, and a JFET region provided between the first body region and the second body region and having a second conductivity type different from the first conductivity type. The JFET region has both a first impurity capable of providing the first conductivity type and a second impurity capable of providing the second conductivity type. A concentration of the second impurity is higher than a concentration of the first impurity. The first conductivity type is p type. The second conductivity type is n type.
A silicon carbide semiconductor device according to one embodiment of the present disclosure includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region being in contact with the gate insulating film at the first main surface and having a first conductivity type, a second body region being in contact with the gate insulating film at the first main surface and having the first conductivity type, a drift region having a second conductivity type different from the first conductivity type, and a JFET region provided between the first body region and the second body region in a direction parallel to the first main surface, provided between the gate insulating film and the drift region in a direction perpendicular to the first main surface, and having the second conductivity type. The JFET region and the drift region each have an impurity capable of providing the second conductivity type. A density of threading dislocations in the first main surface is not less than 100 cm−2 and not more than 10000 cm−2. A concentration of the impurity included in the JFET region is lower than a concentration of the impurity included in the drift region. The first conductivity type is p type. The second conductivity type is n type.
According to the above, a silicon carbide semiconductor device capable of suppressing dielectric breakdown of a gate insulating film can be provided.
A gate insulating film of a planar MOSFET (Metal Oxide Semiconductor Field Effect Transistor), for example, is provided between a gate electrode and a JFET (Junction Field Effect Transistor) region. Thus, when a voltage is applied between a drain electrode and a source electrode, an electric field is concentrated in a portion of the gate insulating film on the JFET region. When the transistor is in an off state, the source electrode has a ground potential (0V), the drain electrode has 1700V applied thereto, for example, and the gate electrode has a ground potential (0V). There is thus a potential difference of about 1700V between the gate electrode and the source electrode. In other words, when the transistor is in an off state, the electric field is concentrated in the gate insulating film. As a result, dielectric breakdown tends to occur in a portion of the gate insulating film on the JFET region.
Accordingly, the present inventors conceived of reducing the intensity of the electric field applied to the gate insulating film provided on the JFET region, by reducing an effective carrier concentration in the JFET region.
Next, embodiments of the present disclosure will be listed and described.
(1) A silicon carbide semiconductor device 1 according one embodiment of the present disclosure includes a silicon carbide substrate 10 and a gate insulating film 15. Silicon carbide substrate 10 has a first main surface 10a and a second main surface 10b opposite to first main surface 10a. Gate insulating film 15 is provided on first main surface 10a. Silicon carbide substrate 10 includes a first body region 13a being in contact with gate insulating film 15 at first main surface 10a and having a first conductivity type, a second body region 13b being in contact with gate insulating film 15 at first main surface 10a and having the first conductivity type, and a JFET region 2 provided between first body region 13a and second body region 13b and having a second conductivity type different from the first conductivity type. JFET region 2 has both a first impurity capable of providing the first conductivity type and a second impurity capable of providing the second conductivity type. A concentration of the second impurity is higher than a concentration of the first impurity. The first conductivity type is p type. The second conductivity type is n type.
In accordance with silicon carbide semiconductor device 1 according to (1) above, JFET region 2 has both the first impurity capable of providing the first conductivity type and the second impurity capable of providing the second conductivity type. Accordingly, carriers of different conductivity types are offset from one another, which can lead to a reduction in effective carrier concentration in the JFET region. Thus, the dielectric breakdown of gate insulating film 15 on JFET region 2 can be suppressed.
(2) In silicon carbide semiconductor device 1 according to (1) above, a density of threading dislocations 3 in first main surface 10a may be not less than 100 cm−2 and not more than 10000 cm−2.
If there are threading dislocations 3 in first main surface 10a, an electric field tends to be concentrated particularly in portions of gate insulating film 15 formed in the vicinity of threading dislocations 3. One possible cause for the electric field concentration is that, during thermal oxidation of main surface 10a in the step of forming gate insulating film 15, pits resulting from threading dislocations 3 increase, causing the electric field to be concentrated in the vicinity of the pits. Another possible cause for the electric field concentration is that the thickness of gate insulating film 15 becomes non-uniform in the vicinity of the pits, which may have caused dielectric breakdown at the thinned portions of gate insulating film 15. By providing gate insulating film 15 on first main surface 10a in which the density of threading dislocations 3 is not less than 100 cm−2 and not more than 10000 cm−2, the dielectric breakdown of gate insulating film 15 formed on threading dislocations 3 can be suppressed.
(3) In silicon carbide semiconductor device 1 according to (1) or (2) above, the concentration of the first impurity may increase from second main surface 10b toward first main surface 10a. Accordingly, the carrier concentration on the second main surface 10b side can be kept at high level while the carrier concentration on the first main surface 10a side is reduced, thereby allowing the on-resistance to be kept at low level.
(4) In silicon carbide semiconductor device 1 according to any one of (1) to (3) above, the first impurity may be aluminum. Since aluminum is less likely to be diffused than the other types of the first impurity, the carrier concentration in the vicinity of first main surface 10a can be accurately reduced.
(5) In silicon carbide semiconductor device 1 according to any one of (1) to (4) above, the concentration of the second impurity may be not less than 1×1014 cm−3 and not more than 1×1016 cm−3.
(6) In silicon carbide semiconductor device 1 according to any one of (1) to (5) above, silicon carbide substrate 10 includes a first cell region CL1 having an outer shape of a polygon as seen along a direction perpendicular to first main surface 10a, and a second cell region CL2 sharing one side M12a of the polygon with first cell region CL1 and having an outer shape of the polygon as seen along the direction perpendicular to first main surface 10a. JFET region 2 may include an end C0 of one side M12a. The dielectric breakdown of a portion of gate insulating film 15 on end C0, where the electric field tends to be concentrated, can thereby be suppressed.
(7) A silicon carbide semiconductor device 1 according one embodiment of the present disclosure includes a silicon carbide substrate 10 and a gate insulating film 15. Silicon carbide substrate 10 has a first main surface 10a and a second main surface 10b opposite to first main surface 10a. Gate insulating film 15 is provided on first main surface 10a. Silicon carbide substrate 10 includes a first body region 13a being in contact with gate insulating film 15 at first main surface 10a and having a first conductivity type, a second body region 13b being in contact with gate insulating film 15 at first main surface 10a and having the first conductivity type, a drift region 12 having a second conductivity type different from the first conductivity type, and a JFET region 2 provided between first body region 13a and second body region 13b in a direction parallel to first main surface 10a, provided between gate insulating film 15 and drift region 12 in a direction perpendicular to first main surface 10a, and having the second conductivity type. JFET region 2 and drift region 12 each have an impurity capable of providing the second conductivity type. A density of threading dislocations 3 in first main surface 10a is not less than 100 cm−2 and not more than 10000 cm−2. A concentration of the impurity included in JFET region 2 is lower than a concentration of the impurity included in drift region 12. The first conductivity type is p type. The second conductivity type is n type.
In accordance with silicon carbide semiconductor device 1 according to (7) above, the concentration of the impurity included in JFET region 2 is lower than the concentration of the impurity included in drift region 12. The on-resistance can thereby be reduced while the dielectric breakdown of gate insulating film 15 on JFET region 2 is suppressed. In addition, by providing gate insulating film 15 on first main surface 10a in which the density of threading dislocations 3 is not less than 100 cm−2 and not more than 10000 cm−2, the dielectric breakdown of gate insulating film 15 formed on threading dislocations 3 can be suppressed.
(8) In silicon carbide semiconductor device 1 according to (7) above, the concentration of the impurity included in JFET region 2 may be not less than 1×1014 cm−3 and not more than 1×1016 cm−3.
(9) In silicon carbide semiconductor device 1 according to (7) or (8) above, in JFET region 2, the concentration of the impurity may decrease from second main surface 10b toward first main surface 10a. The on-resistance can thereby be reduced while the dielectric breakdown of gate insulating film 15 on JFET region 2 is suppressed.
(10) In silicon carbide semiconductor device 1 according to any one of (7) to (9) above, in drift region 12, the concentration of the impurity may decrease from second main surface 10b toward first main surface 10a. The on-resistance can thereby be reduced while the dielectric breakdown of gate insulating film 15 on JFET region 2 is suppressed.
The embodiments of the present disclosure will be described below based on the drawings. It is noted that the same or corresponding parts are designated by the same reference numbers in the following drawings, and description thereof will not be repeated. Regarding crystallographic indications in the present specification, an individual orientation is represented by [ ], a group orientation is represented by < >, an individual plane is represented by ( ), and a group plane is represented by { }. In addition, a negative crystallographic index is normally expressed by putting “-” (bar) above a numeral, but is expressed by putting a negative sign before the numeral in the present specification.
First, the configuration of a MOSFET 1 as a silicon carbide semiconductor device 1 according to a first embodiment of the present disclosure will be described.
As shown in
Silicon carbide substrate 10 mainly has a silicon carbide single-crystal substrate 11, and a silicon carbide epitaxial layer 24 arranged on silicon carbide single-crystal substrate 11. Silicon carbide single-crystal substrate 11 is made of hexagonal silicon carbide having a polytype of 4H, for example. Silicon carbide single-crystal substrate 11 includes an n type impurity such as nitrogen and has n type conductivity (second conductivity type). Silicon carbide substrate 10 has a first main surface 10a constituted by silicon carbide epitaxial layer 24, and a second main surface 10b located opposite to first main surface 10a and constituted by silicon carbide single-crystal substrate 11. First main surface 10a of silicon carbide substrate 10 is a plane angled off by not more than about 8° relative to a {0001} plane, for example, and preferably a plane angled off by not more than about 8° relative to a (0001) plane. Silicon carbide epitaxial layer 24 mainly has a body region 13, a JFET region 2, a drift region 12, a source region 14, and a contact region 18.
Body region 13 includes a p type impurity such as aluminum or boron and has p type conductivity (first conductivity type). The concentration of the p type impurity included in body region 13 is, for example, not less than 1×1016 cm−3 and not more than 1×1018 cm−3. As shown in
JFET region 2 has both a first impurity capable of providing p type (first conductivity type) and a second impurity capable of providing n type (second conductivity type). The first impurity is a p type impurity such as aluminum or boron. The second impurity is an n type impurity such as nitrogen or phosphorus. In JFET region 2, the concentration of the second impurity is higher than the concentration of the first impurity. Thus, JFET region 2 has n type conductivity different from the p type conductivity.
As shown in
Drift region 12 has an n type impurity (second impurity) such as nitrogen and has n type conductivity. Drift region 12 is formed continuously with JFET region 2. The concentration of the n type impurity included in drift region 12 is substantially equal to the concentration of the n type impurity included in JFET region 2. Drift region 12 is provided between JFET region 2 and silicon carbide single-crystal substrate 11, and is provided between body region 13 and silicon carbide single-crystal substrate 11. Drift region 12 has a first drift region 12a, a second drift region 12b and a third drift region 12c.
In
As shown in
As shown in
As shown in
Source region 14 includes an n type impurity such as phosphorus and has n type conductivity. The concentration of the n type impurity included in source region 14 is about 1×1020 cm−3, for example. Source region 14 is separated from both JFET region 2 and drift region 12 by body region 13. The concentration of then type impurity included in source region 14 is higher than the concentration of the n type impurity included in drift region 12. As shown in
Contact region 18 includes a p type impurity such as aluminum and has p type conductivity. The concentration of the p type impurity included in contact region 18 is about 1×1020 cm−3, for example. The concentration of the p type impurity included in contact region 18 is higher than the concentration of the p type impurity included in body region 13. Contact region 18 has a first contact region 18a, a second contact region 18b and a third contact region 18c. It is noted that the elements and concentrations of the n type impurity and p type impurity, as well as the conductivity types of the respective regions described above can be measured by SIMS (Secondary Ion Mass Spectrometry), for example.
As shown in
First cell region CL1 and second cell region CL2 share one side M12a of the polygon. Second cell region CL2 and third cell region CL3 share one side M23a of the polygon. Third cell region CL3 and first cell region CL1 share one side M13a of the polygon. Side M12a, side M23a and side M13a share a triple point C0. First JFET region 2a is in contact with second JFET region 2b at side M12a. Second JFET region 2b is in contact with third JFET region 2c at side M23a. Third JFET region 2c is in contact with first JFET region 2a at side M13a.
As shown in
First cell region CL1 has first JFET region 2a, first drift region 12a, first body region 13a, first source region 14a and first contact region 18a. In plan view, first body region 13a, first source region 14a and first contact region 18a each have a hexagonal outer shape. First contact region 18a is surrounded by first source region 14a. First source region 14a is surrounded by first body region 13a. First body region 13a is surrounded by first JFET region 2a. First source region 14a is separated from first JFET region 2a and first drift region 12a by first body region 13a.
Second cell region CL2 has second JFET region 2b, second drift region 12b, second body region 13b, second source region 14b and second contact region 18b. In plan view, second body region 13b, second source region 14b and second contact region 18b each have a hexagonal outer shape. Second contact region 18b is surrounded by second source region 14b. Second source region 14b is surrounded by second body region 13b. Second body region 13b is surrounded by second JFET region 2b. Second source region 14b is separated from second JFET region 2b and second drift region 12b by second body region 13b.
Third cell region CL3 has third JFET region 2c, third drift region 12c, third body region 13c, third source region 14c and third contact region 18c. In plan view, third body region 13c, third source region 14c and third contact region 18c each have a hexagonal outer shape. Third contact region 18c is surrounded by third source region 14c. Third source region 14c is surrounded by third body region 13c. Third body region 13c is surrounded by third JFET region 2c. Third source region 14c is separated from third JFET region 2c and third drift region 12c by third body region 13c.
As shown in
As shown in
Gate electrode 27 is provided to face channel region CH. Gate electrode 27 is made of a material including polysilicon doped with an impurity, for example. Gate electrode 27 is provided on gate insulating film 15. Gate electrode 27 is provided to face source region 14, body region 13 and JFET region 2. Interlayer insulating film 22 is provided in contact with gate insulating film 15 and gate electrode 27. Interlayer insulating film 22 is provided to cover gate electrode 27, and electrically insulates gate electrode 27 and source electrode 16 from each other. Interlayer insulating film 22 is made of a material including silicon dioxide, for example.
Source electrode 16 has a first source electrode 16a, a second source electrode 16b and a third source electrode. First source electrode 16a is in contact with first source region 14a and first contact region 18a at first main surface 10a of silicon carbide substrate 10. Likewise, second source electrode 16b is in contact with second source region 14b and second contact region 18b at first main surface 10a. Likewise, the third source electrode is in contact with third source region 14c and third contact region 18c at first main surface 10a. Source electrode 16 is made of a material including aluminum, for example. Preferably, source electrode 16 is made of a material including TiAlSi. Source line 19 is provided in contact with source electrode 16. Source line 19 is provided to cover interlayer insulating film 22.
Drain electrode 20 is provided in contact with second main surface 10b of silicon carbide substrate 10. Drain electrode 20 is made of a material capable of making ohmic contact with n type silicon carbide single-crystal substrate 11, such as NiSi, and is electrically connected to silicon carbide single-crystal substrate 11.
The density of threading dislocations 3 in first main surface 10a is not less than 100 cm−2 and not more than 10000 cm−2, for example. An upper limit value of the density of threading dislocations 3 may be 5000 cm−2, for example. A lower limit value of the density of threading dislocations 3 may be 200 cm−2, for example. Threading dislocations 3 include threading edge dislocations and threading screw dislocations, for example. Threading dislocations 3 extend from first main surface 10a to second main surface 10b of silicon carbide substrate 10, for example. In other words, threading dislocations 3 are formed in silicon carbide epitaxial layer 24 and silicon carbide single-crystal substrate 11. Threading dislocations 3 may thread through drift region 12 and JFET region 2. From the perspective of suppressing dielectric breakdown of gate insulating film 15, the density of threading dislocations 3 in the surface of JFET region 2 in contact with gate insulating film 15 may be not less than 100 cm−2 and not more than 10000 cm−2.
Next, a method of measuring the density of threading dislocations will be described.
First, the silicon carbide semiconductor device covered by a resin package is immersed in fuming nitric acid to remove the resin package. Then, an Al (aluminum) line and a Cu (copper) lead frame are removed with HCl (hydrochloric acid). Interlayer insulating film 22, gate electrode 27 and gate insulating film 15 are removed with a mixed solution of HNO3 (nitric acid) and HF (hydrofluoric acid). First main surface 10a of silicon carbide substrate 10 is thereby exposed. If a semiconductor chip is not covered by a resin package, the step of removing the resin package is not required.
Next, first main surface 10a of silicon carbide substrate 10 is etched with molten KOH (potassium hydroxide). The concentration of KOH is 100%, for example. The temperature of KOH is 500° C., for example. The etching period is 5 minutes, for example. Silicon carbide substrate 10 is etched by about a few hundred nm, for example. Etch pits resulting from the threading dislocations are formed in this manner.
Next, the etch pits are observed with the Olympus industrial inspection microscope (MX51). The microscope magnification is not less than 500 times and not more than 1000 times, for example. A dark field is better suited for observation than a bright field. The inspection area is desirably larger than 1 cm×1 cm, for example. In plan view, an etch pit having a hexagonal outer shape is determined to be a threading dislocation. In other words, the density of threading dislocations is determined by measuring the area density of etch pits.
Next, the operation of the MOSFET will be described. As shown in
Next, the configuration of a variation of
As shown in
First cell region CL1 has first JFET region 2a, first drift region 12a, first body region 13a, first source region 14a and first contact region 18a. In plan view, first body region 13a, first source region 14a and first contact region 18a each have a rectangular outer shape. First contact region 18a is provided between a pair of first source regions 14a. First source region 14a is provided between first body region 13a and first contact region 18a. First body region 13a is provided between first JFET region 2a and first source region 14a.
Second cell region CL2 has second JFET region 2b, second drift region 12b, second body region 13b, second source region 14b and second contact region 18b. In plan view, second body region 13b, second source region 14b and second contact region 18b each have a rectangular outer shape. Second contact region 18b is provided between a pair of second source regions 14b. Second source region 14b is provided between second body region 13b and second contact region 18b. Second body region 13b is provided between second JFET region 2b and second source region 14b. A portion provided between first body region 13a and second body region 13b forms JFET region 2.
Next, a method of manufacturing MOSFET 1 according to the first embodiment will be described.
First, a step of preparing a silicon carbide substrate (S10:
As shown in
Next, ion implantation is performed into first main surface 10a of silicon carbide epitaxial layer 24. Ions of a p type impurity such as aluminum are implanted into silicon carbide epitaxial layer 24. First body region 13a, second body region 13b and third body region 13c are thereby formed. Then, ions of an n type impurity such as phosphorus are implanted into each of first body region 13a, second body region 13b and third body region 13c. First source region 14a, second source region 14b and third source region 14c are thereby formed. Then, ions of a p type impurity such as aluminum are implanted into each of first source region 14a, second source region 14b and third source region 14c. First contact region 18a, second contact region 18b and third contact region 18c are thereby formed. A region provided between first body region 13a and second body region 13b serves as JFET region 2 (see
Next, a mask layer 4 is formed on first main surface 10a. Mask layer 4 has an opening above JFET region 2. As shown in
Next, an activation annealing step is performed. Specifically, heat treatment is performed in which silicon carbide substrate 10 is heated to about 1700° C., for example, and held for about 30 minutes in an atmosphere of inert gas such as argon. The ion implanted impurities are thereby activated.
Next, a step of forming a gate insulating film (S20:
Next, a nitrogen annealing step may be performed. Specifically, silicon carbide substrate 10 is held at a temperature of about 1100° C. for about one hour, for example, in a nitrogen monoxide atmosphere. Then, heat treatment may be performed in which silicon carbide substrate 10 is heated in inert gas such as argon or nitrogen. Silicon carbide substrate 10 is held at a temperature of not less than 1100° C. and not more than 1500° C. for about one hour in an argon atmosphere, for example.
Next, a step of forming a gate electrode (S30:
Next, a step of forming an interlayer insulating film (S40:
Next, a step of forming a source electrode (S50:
Next, source line 19 made of a material including aluminum, for example, is formed to make contact with source electrode 16. Then, drain electrode 20 is formed in contact with second main surface 10b of silicon carbide single-crystal substrate 11. Drain electrode 20 includes NiSi, for example. MOSFET 1 shown in
Next, the function and effect of MOSFET 1 according to the first embodiment will be described.
In accordance with MOSFET 1 according to the first embodiment, JFET region 2 has both the first impurity capable of providing the first conductivity type and the second impurity capable of providing the second conductivity type. Accordingly, carriers of different conductivity types are offset from one another, which can lead to a reduction in effective carrier concentration in the JFET region. Thus, the dielectric breakdown of gate insulating film 15 on JFET region 2 can be suppressed.
In accordance with MOSFET 1 according to the first embodiment, the density of threading dislocations 3 in first main surface 10a is not less than 100 cm−2 and not more than 10000 cm−2. If there are threading dislocations 3 in first main surface 10a, an electric field tends to be concentrated particularly in portions of gate insulating film 15 formed in the vicinity of threading dislocations 3. One possible cause for the electric field concentration is that, during thermal oxidation of main surface 10a in the step of forming gate insulating film 15, pits resulting from threading dislocations 3 increase, causing the electric field to be concentrated in the vicinity of the pits. Another possible cause for the electric field concentration is that the thickness of gate insulating film 15 becomes non-uniform in the vicinity of the pits, which may have caused dielectric breakdown at the thinned portions of gate insulating film 15. By providing gate insulating film 15 on first main surface 10a in which the density of threading dislocations 3 is not less than 100 cm−2 and not more than 10000 cm−2, the dielectric breakdown of gate insulating film 15 formed on threading dislocations 3 can be suppressed.
Furthermore, in accordance with MOSFET 1 according to the first embodiment, the concentration of the first impurity increases from second main surface 10b toward first main surface 10a. Accordingly, the carrier concentration on the second main surface 10b side can be kept at high level while the carrier concentration on the first main surface 10a side is reduced, thereby allowing the on-resistance to be kept at low level.
Furthermore, in accordance with MOSFET 1 according to the first embodiment, the first impurity is aluminum. Since aluminum is less likely to be diffused than the other types of the first impurity, the carrier concentration in the vicinity of first main surface 10a can be accurately reduced.
Furthermore, in accordance with MOSFET 1 according to the first embodiment, the concentration of the second impurity is not less than 1×1014 cm−3 and not more than 1×1016 cm−3.
Furthermore, in accordance with MOSFET 1 according to the first embodiment, silicon carbide substrate 10 includes first cell region CL1 having an outer shape of a polygon as seen along the direction perpendicular to first main surface 10a, and second cell region CL2 sharing one side M12a of the polygon with first cell region CL1 and having an outer shape of the polygon as seen along the direction perpendicular to first main surface 10a. JFET region 2 may include end C0 of one side M12a. The dielectric breakdown of a portion of gate insulating film 15 on end C0, where the electric field tends to be concentrated, can thereby be suppressed.
Next, the configuration of MOSFET 1 as silicon carbide semiconductor device 1 according to a second embodiment of the present disclosure will be described. MOSFET 1 according to the second embodiment is mainly different from MOSFET 1 according to the first embodiment in that the concentration of the impurity included in JFET region 2 is lower than the concentration of the impurity included in drift region 12, and is otherwise substantially the same in configuration as MOSFET 1 according to the first embodiment. Thus, the same or corresponding parts are designated by the same reference numbers and description thereof will not be repeated.
As shown in
In
As shown in
As shown in
In the step of forming a silicon carbide epitaxial layer described in the first embodiment (see
Although a MOSFET has been described as an example of the silicon carbide semiconductor device in the embodiments described above, the silicon carbide semiconductor device may be an IGBT (Insulated Gate Bipolar Transistor) or the like.
Next, the function and effect of MOSFET 1 according to the second embodiment will be described.
In accordance with MOSFET 1 according to the second embodiment, the concentration of the impurity included in JFET region 2 is lower than the concentration of the impurity included in drift region 12. The on-resistance can thereby be reduced while the dielectric breakdown of gate insulating film 15 on JFET region 2 is suppressed. In addition, by providing gate insulating film 15 on first main surface 10a in which the density of threading dislocations 3 is not less than 100 cm−2 and not more than 10000 cm−2, the dielectric breakdown of gate insulating film 15 formed on threading dislocations 3 can be suppressed.
In accordance with MOSFET 1 according to the second embodiment, the concentration of the impurity included in JFET region 2 is not less than 1×1014 cm−3 and not more than 1×1016 cm−3.
Furthermore, in accordance with MOSFET 1 according to the second embodiment, in JFET region 2, the concentration of the impurity may decrease from second main surface 10b toward first main surface 10a. The on-resistance can thereby be reduced while the dielectric breakdown of gate insulating film 15 on JFET region 2 is suppressed.
Furthermore, in accordance with MOSFET 1 according to the second embodiment, in drift region 12, the concentration of the impurity may decrease from second main surface 10b toward first main surface 10a. The on-resistance can thereby be reduced while the dielectric breakdown of gate insulating film 15 on JFET region 2 is suppressed.
It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
1 MOSFET (silicon carbide semiconductor device); 2 JFET region; 2a first JFET region; 2b second JFET region; 2c third JFET region; 3 threading dislocation; 4 mask layer; 10 silicon carbide substrate; 10a first main surface (main surface); 10b second main surface; 11 silicon carbide single-crystal substrate; 11a, 11b surface; 12 drift region; 12a first drift region; 12b second drift region; 12c third drift region; 13 body region; 13a first body region; 13b second body region; 13c third body region; 14 source region; 14a first source region; 14b second source region; 14c third source region; 15 gate insulating film; 16 source electrode; 16a first source electrode; 16b second source electrode; 18 contact region; 18a first contact region; 18b second contact region; 18c third contact region; 19 source line; 20 drain electrode; 22 interlayer insulating film; 24 silicon carbide epitaxial layer; 27 gate electrode; C0 end (triple point); CH channel region; CL1 first cell region; CL2 second cell region; CL3 third cell region; M12a, M13a, M23a one side, side; P1 first portion; P2 second portion; P3 third portion.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-031789 | Feb 2015 | JP | national |
This application is a Divisional of U.S. patent application Ser. No. 15/552,170, filed Aug. 18, 2017, which is a 371 application of International Application No. PCT/JP2016/053946, filed Feb. 10, 2016, which claims the benefit of Japanese Patent Application No. 2015-031789, filed Feb. 20, 2015.
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| Number | Date | Country | |
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| Number | Date | Country | |
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| Child | 16220501 | US |
