Patent Application
20110284873
The present invention relates to a silicon carbide substrate.
Recently, a SiC (silicon carbide) substrate has been introduced as a semiconductor substrate used for manufacturing semiconductor devices. As compared with more widely used Si (silicon), SiC has wider bandgap. Therefore, a semiconductor device using a SiC substrate has advantages such as high breakdown voltage and low on-resistance and, in addition, its property does not much degrade in high-temperature environment.
In order to enable efficient manufacturing of semiconductor devices, the substrate must be of a certain size or larger. According to U.S. Pat. No. 7,314,520 (Patent Document 1), it is possible to manufacture a SiC substrate having the size of at least 76 mm (3 inches).
Industrially available size of SiC single crystal substrate is about 100 mm (4 inches) at the largest and, therefore, it has been difficult to efficiently manufacture semiconductor devices by using a large single-crystal substrate. When characteristics of a plane other than the (0001) plane are to be utilized in hexagonal system SiC, this poses a particularly serious problem. This will be discussed in the following.
A SiC single crystal substrate with a very small number of defects is typically manufactured by cutting a SiC ingot obtained through surface growth of the (0001) plane that is less susceptible to stacking fault. Therefore, it follows that a single crystal substrate having plane orientation other than the (0001) plane is cut not parallel to the surface of growth. As a result, it becomes difficult to ensure the full size of single crystal substrate, or to effectively make use of large part of the ingot. Consequently, it is particularly difficult to manufacture with high efficiency semiconductor devices utilizing a plane other than the (0001) plane of SiC.
As an alternative to the effort of enlarging the size of SiC single crystal substrate involving difficulties, use of a silicon carbide substrate having a support portion and a plurality of small single crystal substrates joined thereon has been considered. The silicon carbide substrate can be made larger as needed by increasing the number of single crystal substrates.
However, the silicon carbide substrate having the support portion and single crystal substrates joined to each other as described above is susceptible to warpage and, possibly, cracks, because of differences in property between the single crystal substrate and the support portion.
The present invention was made in view of the foregoing, and its object is to provide a silicon carbide substrate having a support portion and a single crystal substrate joined to each other, which is less prone to warpage.
The silicon carbide substrate in accordance with the present invention has a substrate region and a support portion. The substrate region has a first single crystal substrate. The first single crystal substrate has a first front-side surface and a first backside surface opposite to each other and a first side surface connecting the first front-side surface and the first backside surface. The support portion is joined to the first backside surface. The dislocation density of the first single crystal substrate is lower than the dislocation density of the support portion. At least one of the substrate region and the support portion has voids.
According to the present invention, since the dislocation density of the first single crystal substrate is lower than the dislocation density of the support portion, extremely high crystal quality of silicon carbide substrate can be attained in the first single crystal substrate. Further, since stress in the silicon carbide substrate is alleviated by voids, warpage of the silicon carbide substrate can be reduced.
Preferably, the number of voids per unit volume in the support portion is larger than in the first single crystal substrate. The number of voids in the first single crystal substrate is made small while the number of voids in the support portion is made larger, so that sufficiently large number of voids to alleviate stress can be provided. Thus, warpage of the silicon carbide substrate can be reduced without lowering the quality of first single crystal substrate.
Preferably, the first single crystal substrate has a first concentration as impurity concentration per unit volume, the support portion has a second concentration as impurity concentration per unit volume, and the second concentration is higher than the first concentration. Therefore, electric resistance of the support portion can be made lower.
Preferably, the substrate region includes a second single crystal substrate. The second single crystal substrate has a second front-side surface and a second backside surface opposite to each other and a second side surface connecting the second front-side surface and the second backside surface. The second backside surface is joined to the support portion. Since both the first and second front-side surfaces are provided as the surfaces of substrate region, the surface area of silicon carbide substrate can be increased.
Preferably, the substrate region includes a space portion positioned between the first and second side surfaces facing each other. The space portion has a filled portion partially filling the space portion. Therefore, deposition of foreign matter in the space portion can be reduced than when the filled portion is not provided.
Preferably, the first single crystal substrate has a first porosity, and the space portion has a second porosity. The second porosity is higher than the first porosity. Deformation of the space portion promotes stress alleviation. Thus, warpage of the silicon carbide substrate can further be reduced.
Preferably, the substrate region includes a third single crystal substrate. The third single crystal substrate is joined to the first front-side surface of the first single crystal substrate. Thus, the substrate region comes to have a stacked structure.
Preferably, the number of voids per unit volume in the support potion is at least 10 cm−3. Thus, warpage of the silicon carbide substrate can further be reduced.
Preferably, the number of voids relates to voids whose volume is at least 1 μm3. Thus, warpage of the silicon carbide substrate can more reliably be reduced.
Preferably, the first front-side surface has an off angle of at least 50° and at most 65° with respect to the {0001} plane. More preferably, an angle formed by off orientation of the first front-side surface and <1-100> direction of the first single crystal substrate is at most 5°. Further preferably, off angle of the first front-side surface with respect to the {03-38} plane in <1-100> direction of the first single crystal substrate is at least −3° and at most 5°. Thus, channel mobility of the first front-side surface can be improved than when the first front-side surface is the {0001} plane.
Preferably, the first front-side surface has an off angle of at least 50° and at most 65° with respect to the {0001} plane. An angle formed by off orientation of the first front-side surface and <11-20> direction of the first single crystal substrate is at most 5°. Thus, channel mobility of the first front-side surface can be improved than when the first front-side surface is the {0001} plane.
Preferably, the first backside surface of the first single crystal substrate is formed by slicing. Specifically, the first backside surface is formed by slicing and not subjected to polishing thereafter. Thus, the first backside surface has ups and downs. The space in the concave portions of the ups and downs can be used as gaps in which sublimation gas accumulates, when the support portion is provided on the first backside surface by sublimation.
As is apparent from the description above, the present invention provides a silicon carbide substrate having a support portion and a single crystal substrate joined to each other, which is less prone to warpage.
In the following, embodiments of the present invention will be described with reference to the figures.
Referring to
Single crystal substrate 11 (first single crystal substrate) has a first front-side surface F1 and a first backside surface B1 opposite to each other, and a first side surface S1 connecting the first front-side surface F1 and the first backside surface B1. Single crystal substrate 12 (second single crystal substrate) has a second front-side surface F2 and a second backside surface B2 opposite to each other, and a second side surface S2 connecting the second front-side surface F2 and the second backside surface B2. The first and second single crystal substrates are arranged such that the first and second side surfaces S1 and S2 face each other with a space GP therebetween. The shortest distance between the first and second side surfaces is preferably at most 5 mm, more preferably at most 1 mm, further preferably at most 100 and most preferably at most 10 μm.
The front-side surface of each of single crystal substrates 11 to 19 preferably has the plane orientation of {03-38}. It is noted, however, that {0001}, {11-20} or {1-100} may be used as the plane orientation. Further, a plane off from each of the above-mentioned plane orientation by a few degrees may also be used.
Filled portion 20 fills a part of space GP to connect the first and second front-side surfaces F1 and F2. Since space GP has relatively large void V1a as shown in
Support portion 30 is joined to each of single crystal substrates 11 to 19, for example, to each of the first and second backside surfaces B1 and B2. Support portion 30 has, for example, a disk-shape, of which diameter is preferably at least 50 mm, and more preferably, at least 150 mm.
The number of voids per unit volume is larger in support portion 30 than in each of single crystal substrates 11 to 19. Preferably, the number of voids per unit volume in support portion 30 is at least 10 cm−3. Here, the number of voids refers to the number of voids having a certain volume or larger, and the volume is, for example, 1 μm3.
Further, the dislocation density of each of single crystal substrates 11 to 19 is lower than the dislocation density of support portion 30. Specifically, crystal quality is higher in single crystal substrates 11 to 19 than in support portion 30.
Preferably, each of single crystal substrates 11 to 19 has a first concentration as impurity concentration per unit volume, and support portion 30 has a second concentration as the impurity concentration per unit volume. The second concentration is higher than the first concentration.
Next, the method of manufacturing silicon carbide substrate 81 will be described. For simplicity of description, in the following, only the single crystal substrates 11 and 12 may be referred to among single crystal substrates 11 to 19. It is noted, however, that single crystal substrates 13 to 19 are processed in the same manner as single crystal substrates 11 and 12.
Referring to
Thereafter, first heating body 91, the group 10 of single crystal substrates, support portion 30 and second heating body 92 are arranged stacked in this order. Specifically, first, single crystal substrates 11 to 19 are arranged in a matrix on first heating body 91. By way of example, single crystal substrates 11 and 12 are arranged such that the first and second side surfaces S1 and S2 face each other with a space GP therebetween. Then, on the surfaces of group 10 of single crystal substrates, support portion 30 is placed. Thereafter, on support portion 30, second heating body 92 is placed. Thereafter, the first heating body, the group 10 of single crystal substrates, support portion 30 and the second heating body 92 stacked one after another are housed in heat-insulating container 40 provided with heater 50.
Next, the atmosphere in heat-insulating container 40 is set to a reduced pressure atmosphere. Pressure of the atmosphere is set to be higher than 10−1 Pa and lower than 104 Pa.
The atmosphere described above may be an inert gas atmosphere. As the inert gas, rare gas such as He or Ar, nitrogen gas, or a mixed gas of rare gas and nitrogen gas may be used. When the mixed gas is used, the ratio of nitrogen gas is, for example, 60%. The pressure in heat-insulating container 40 is preferably at most 50 kPa, and more preferably at most 10 kPa.
Thereafter, by heater 50, the group 10 of single crystal substrates and support portion 30 are heated to a temperature that causes sublimation and re-crystallization reaction, through first and second heating bodies 91 and 92. Heating is done to produce temperature difference such that the temperature of support portion 30 becomes higher than the temperature of group 10 of single crystal substrates.
Referring to
When the temperature of support portion 30 is made higher than that of each of single crystal substrates 11 and 12 as described above, material movement occurs because of sublimation, in gap GQ as indicated by an arrow Mc. Further, material movement occurs because of sublimation from support portion 30 to space GP, as indicated by an arrow Mb. Further, material movement occurs because of sublimation in space GP as indicated by an arrow Ma, from the side of backside surface (upper side in the figure) to the side of front-side surface (lower side in the figure) of each of single crystal substrates 11 and 12.
Further, referring to
Further, referring to
Further, by the movement of cavity corresponding to space GP indicated by arrows H1a and H1b (
As the heating continues, voids V1a, V1b and Vc move as indicated by arrows H2a, H2b and H2c, respectively. Thus, silicon carbide substrate 81 shown in
According to the present embodiment, since the dislocation density of each of single crystal substrates 11 to 19 is lower than the dislocation density of support portion 30, crystal quality of silicon carbide substrate can be made particularly higher in each of single crystal substrates 11 to 19. Further, since stress in silicon carbide substrate is alleviated by voids V1 and Vc, warpage of silicon carbide substrate 81 can be reduced.
Further, the number of voids per unit volume is larger in support portion 30 than in each of single crystal substrates 11 to 19. Therefore, it is possible to surely provide sufficiently large number of voids to alleviate stress by increasing the number of voids in support portion 30 while holding down the number of voids in each of single crystal substrates 11 to 19. Thus, warpage of silicon carbide substrate 81 can be reduced without degrading the quality of single crystal substrates 11 to 19.
Further, since first and second front-side surfaces F1 and F2 (
Further, space GP has filled portion 20 partially filling space GP to connect the first and second front-side surfaces F1 and F2. Thus, deposition of foreign matter in space GP can be prevented.
Further, since the porosity of space GP (second porosity) is higher than the porosity of single crystal substrate 11 (first porosity), filled portion 20 is more susceptible to deformation. This means that stress can more easily be alleviated by filled portion 20 and, hence, warpage of silicon carbide substrate 81 can further be reduced. Preferably, the porosity of space GP is made larger than the porosity of each of other single crystal substrates 12 to 19.
Preferably, single crystal substrate 11 has a first concentration as impurity concentration per unit volume, and support portion 30 has a second concentration as the impurity concentration per unit volume. The second concentration is higher than the first concentration. Thus, electric resistance of support portion 30 can be made lower.
Preferably, the number of voids per unit volume in support portion 30 is at least 10 cm−3. Thus, warpage of silicon carbide substrate 81 can further be reduced.
Preferably, the number of voids mentioned above represents the number of voids having the volume of at least 1 μm3. Thus, warpage of silicon carbide substrate 81 can further be reduced.
Preferably, each of single crystal substrates 11 to 19 has the SiC crystal structure of 4H polytype. Hence, silicon carbide substrate 81 suitable for the manufacture of power semiconductor can be obtained.
Preferably, in order to prevent cracking of silicon carbide substrate 81, difference in coefficient of thermal expansion between support portion 30 and single crystal substrates 11 to 19 is made as small as possible in silicon carbide substrate 81. Thus, warpage of silicon carbide substrate 81 can further be reduced. For this purpose, support portion 30 may be adapted, for example, to have the same crystal structure as that of single crystal substrates 11 to 19.
Preferably, in-plane variation of thickness of support portion 30 and each of the group 10 of single crystal substrates (
Electric resistance of support portion 30 prepared before heat treatment is set preferably lower than 50 mΩ·cm and more preferably lower than 10 mΩ·cm.
The impurity concentration of support portion 30 of silicon carbide substrate 81 is preferably set to at least 5×1018 cm−3, and more preferably at least 1×1020 cm−3. When a vertical semiconductor device in which current is caused to flow in the vertical direction such as a vertical MOSFET (Metal Oxide Field Effect Transistor) is manufactured using silicon carbide substrate 81 as such, on-resistance of the vertical semiconductor device can be reduced.
The average electric resistance of silicon carbide substrate 81 is preferably at most 5 mΩ·cm, and more preferably, at most 1 mΩ·cm.
Preferably, the thickness of silicon carbide substrate 81 (dimension in the vertical direction in
Preferably, the first front-side surface F1 has an off angle of at least 50° and at most 65° with respect to the {0001} plane. Consequently, channel mobility at the first front-side surface F1 can be improved than when the first front-side surface is the {0001} plane. More preferably, either the first or second condition below is satisfied.
Under the first condition, an angle formed by the off orientation of first front-side surface F1 and the <1-100> direction of single crystal substrate 11 is at most 5°. More preferably, the off angle of first front-side surface F1 with respect to the {03-38} plane in the <1-100> direction of single crystal substrate 11 is at least −3° and at most 5°.
Under the second condition, an angle formed by the off orientation of first front-side surface F1 and the <11-20> direction of single crystal substrate 11 is at most 5°.
Though the preferable orientation of first front-side surface F1 of single crystal substrate 11 has been described in the foregoing, the same applies to the surface orientation of each of the remaining single crystal substrates 12 to 19.
Mainly referring to
Except for this point, the structure is substantially the same as that of Embodiment 1 described above. Therefore, the same or corresponding elements are denoted by the same reference characters and description thereof will not be repeated. The present embodiment also attains effects similar to those attained by Embodiment 1.
Mainly referring to
The material of filled portion 21 may include, for example, silicon carbide (SiC), silicon (Si), adhesive, resist, resin or silicon oxide (SiO2).
Except for this point, the structure is substantially the same as that of Embodiment 1 described above. Therefore, the same or corresponding elements are denoted by the same reference characters and description thereof will not be repeated. The present embodiment also attains effects similar to those attained by Embodiment 1.
Referring to
A modification of the present embodiment will be described with reference to
Except for this point, the structure is substantially the same as that of Embodiment 1 described above. Therefore, the same or corresponding elements are denoted by the same reference characters and description thereof will not be repeated. The present embodiment also attains effects similar to those attained by Embodiment 1.
Referring to
Except for this point, the structure is substantially the same as that of Embodiment 1 described above. Therefore, the same or corresponding elements are denoted by the same reference characters and description thereof will not be repeated. The present embodiment also attains effects similar to those attained by Embodiment 1.
Referring to
Referring to
In the present embodiment, silicon carbide substrate 81 has n-type conductivity and, as described in Embodiment 1, it has support portion 30 and single crystal substrate 11. Drain electrode 112 is provided on support portion 30 such that support portion 30 is positioned between the drain electrode and single crystal substrate 11. Buffer layer 121 is provided on single crystal substrate 11 such that single crystal substrate 11 is positioned between the buffer layer and support portion 30.
Buffer layer 121 has n-type conductivity, and its thickness is, for example, 0.5 μm. The concentration of n-type conductive impurity in buffer layer 121 is, for example, 5×1017 cm−3.
Breakdown voltage holding layer 122 is formed on buffer layer 121, and it is formed of silicon carbide having n-type conductivity. The thickness of breakdown voltage holding layer 122 is 10 μm, and the concentration of n-type conductive impurity is 5×1015 cm−3.
On a surface of breakdown voltage holding layer 122, a plurality of p-regions 123 having p-type conductivity are formed spaced apart from each other. In p-region 123, an n+ region 124 is formed at a surface layer of p-region 123. A p+ region 125 is formed at a position next to n+ region 124. Extending from above n+ region 124 on one p-region 123 over breakdown voltage holding layer 122 exposed between two p-regions 123, the other p-region 123 and above n+ region 124 in the said the other p-region 123, oxide film 126 is formed. On oxide film 126, gate electrode 110 is formed. Further, on n+ region 124 and p+ region 125, source electrode 111 is formed. On source electrode 111, an upper source electrode 127 is formed.
In a region within 10 nm from the interface between oxide film 126 and each of the semiconductor layers, that is, n+ region 124, p+ region 125, p-region 123, and breakdown voltage holding layer 122, the highest concentration of nitrogen atoms is at least 1×1021 cm−3. Therefore, mobility particularly at the channel region below oxide film 126 (the portion of p-region 123 in contact with oxide film 126 between n+ region 124 and breakdown voltage holding layer 122) can be improved.
Next, the method of manufacturing semiconductor device 100 will be described. Though process steps only in the vicinity of single crystal substrate 11 among single crystal substrates 11 to 19 (
First, at the substrate preparation step (step S110:
Referring to
First, on a surface of single crystal substrate 11 of silicon carbide substrate 81, buffer layer 121 is formed. Buffer layer 121 is formed on silicon carbide having n-type conductivity and, by way of example, it is an epitaxial layer of 0.5 μm in thickness. Further, concentration of conductive impurity in buffer layer 121 is, for example, 5×1017 cm−3.
Next, breakdown voltage holding layer 122 is formed on buffer layer 121. Specifically, a layer formed of silicon carbide having n-type conductivity is formed by epitaxial growth. The thickness of breakdown voltage holding layer 122 is, for example, 10 μm. Concentration of n-type conductive impurity in breakdown voltage holding layer 122 is, for example, 5×1015 cm−3.
Referring to
First, p-type impurity is selectively introduced to a part of breakdown voltage holding layer 122, so that p-region 123 is formed. Next, n-type conductive impurity is selectively introduced to a prescribed region to form n+ region 124, and p-type conductive impurity is selectively introduced to a prescribed region to form p+ region 125. Selective introduction of impurities is done using a mask formed, for example, of an oxide film.
Following the implantation step as such, an activation annealing treatment is done. By way of example, annealing is done in an argon atmosphere, at a heating temperature of 1700° C. for 30 minutes.
Referring to
Thereafter, the nitrogen annealing step (step S150) is done. Specifically, annealing is done in a nitrogen monoxide (NO) atmosphere. Conditions for this process are, for example, heating temperature of 1100° C. and heating time of 120 minutes. As a result, nitrogen atoms are introduced to the vicinity of interface between each of breakdown voltage holding layer 122, p-region 123, n+ region 124 and p+ region 125 and oxide film 126.
Following the annealing step using nitrogen monoxide, annealing using argon (Ar) gas as an inert gas may be performed. Conditions for the process are, for example, heating temperature of 1100° C. and heating time of 60 minutes.
Referring to
First, on oxide film 126, using photolithography, a resist film having a pattern is formed. Using the resist film as a mask, portions of oxide film 126 positioned on n+ region 124 and p+ region 125 are removed by etching. Thus, openings are formed in oxide film 126. Next, a conductive film is formed to be in contact with each of n+ region 124 and p′ region 125 in the openings. Then, the resist film is removed, whereby portions of the conductive film that have been positioned on the resist film are removed (lift off). The conductive film may be a metal film and, by way of example, it is formed of nickel (Ni). As a result of this lift off, source electrode 111 is formed.
Here, heat treatment for alloying is preferably carried out. By way of example, heat treatment is done in an atmosphere of argon (Ar) gas as an inert gas, at a heating temperature of 950° C. for 2 minutes.
Again referring to
It is noted that a structure having conductivity types reversed from the present embodiment, that is, p-type and n-type reversed, may be used.
Further, the silicon carbide substrate for fabricating semiconductor device 100 is not limited to silicon carbide substrate 81 in accordance with Embodiment 1, and it may be any of silicon carbide substrates 82 to 86 (Embodiments 2 to 6).
Further, though a vertical DiMOSFET has been described as an example, other semiconductor devices may be manufactured using the semiconductor substrate in accordance with the present invention. For instance, a RESURF-JFET (Reduced Surface Field-Junction Field Effect Transistor) or a Schottky diode may be manufactured.
As support portion 30 (
Single crystal substrates 11 to 19 were arranged in a matrix on the first heating body 91. On the group 10 of single crystal substrates, support portion 30 was placed. Then, the second heating body 92 was placed on support portion 30. In this manner, a stacked body consisting of first heating body 91, group 10 of single crystal substrates, support portion 30 and second heating body 92 was prepared.
The stacked body described above was housed in heat-insulating container 40 (
The number of voids per unit volume of support portion 30 of silicon carbide substrate 81 was 10 cm−3 or higher. Further, impurity concentration in support portion 30 was 5×1020 cm−3. Specifically, the impurity concentration of support portion 30 after heat treatment was made higher than the value 1×1020 cm−3 before heat treatment. The reason for this is considered that support portion 30 took in nitrogen in the atmosphere described above.
A cross-section of silicon carbide substrate 81 was inspected by an SEM (Scanning Electron Microscope), and it was found that gaps GQ (
In the present example, the temperature of single crystal substrate 11 was made lower than the temperature of support portion 30 in the heat treatment, while an experiment of heat treatment without such temperature difference was conducted. As a result, it was found that more gaps GQ were left as compared with the example of the invention.
As further samples of the inventive example, silicon carbide substrates having the diameters of 50 mm, 75 mm, 100 mm, 125 mm and 150 mm were fabricated for each of plane orientations (0001) and (03-38), by the same method as described above. As comparative examples, substrates formed of single crystal corresponding to the dimensions mentioned above were prepared. Each of these substrates was subjected to ion implantation and activation annealing. Conditions for activation annealing were: atmosphere was Ar atmosphere; pressure was 90 kPa; heat increase rate was 100° C./min; temperature was 1800° C.; and holding time was 30 minutes.
Warpage of each of the substrates obtained in the above-described manner was measured. The results were as shown in Table 1.
The results indicated that warpage of substrates could be reduced in the samples of the invention.
Further, probability of cracking of each of the substrates was measured. The results were as shown in Table 2.
The results indicated that probability of cracking could be reduced in the samples of the invention.
Though Ar atmosphere was used for activation annealing in the examples above, similar results were observed when other inert gas atmosphere such as He or N2 gas atmosphere was used.
Correlation between the number of voids per unit volume in support portion 30 of silicon carbide substrate 81 and the warpage of substrate was studied. It was found that the smaller the number of voids per unit volume, the larger became the warpage of substrate. Further, it was found that crack was sometimes observed when the number of voids having the volume of 1 μm3 or larger per unit volume was smaller than 10 cm−3.
The embodiments as have been described here are mere examples and should not be interpreted as restrictive. The scope of the present invention is determined by each of the claims with appropriate consideration of the written description of the embodiments and embraces modifications within the meaning of, and equivalent to, the languages in the claims.
11 single crystal substrate (first single crystal substrate), 12 single crystal substrate (second single crystal substrate), 13-19 single crystal substrates, 20 filled portion, 30 support portion, 41 single crystal substrate (third single crystal substrate), 81-86 silicon carbide substrates, 91 first heating body, 92 second heating body, 100 semiconductor device, R1, R3-R6 substrate regions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2009-285239 | Dec 2009 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2010/066809 | 9/28/2010 | WO | 00 | 7/27/2011 |
