Patent Application
20080166878
This invention relates to fabrication of nanostructures on silicon substrates to facilitate growth of continuous, low-defect GaN and SiC films formed on silicon substrates for use in power devices, and specifically to a method of fabrication of nanostructures having substantially parallel vertical surfaces.
Small whiskers, also called nanorods, or nanowires, and nanotubes, are of increasing interest due to their physical properties as well as their potential for new nanodevices, such as nanowire field effect transistors, nanosilicon photonics, nano-Si substrates for III-V and SiC devices for LED, high power, and MEMs etc., device applications. Comprehensive studies on the vapor-liquid-solid (VLS) growth of whiskers of silicon, and other materials, with sizes in the 100 nm range began in the 1960's and 1970's. However, fabrication of such devices having well defined radius, position, length, and technological applications, was elusive at that time. Several growth concepts have been developed for semiconductors, ceramics, and metals, allowing the fabrication of whiskers with diameters of 100 nm and length of several micrometers.
Silicon whiskers are normally grown by chemical vapor deposition (CVD), gas-source molecular-beam epitaxy (GS-MBE), and by more recently developed electrochemical wet etching processes, however, CVD and GS-MBE are expensive processes, and are not easily able to provide precise control of nanowire position, distribution and orientation, and present difficulties in removal of any catalysts used to promote nanowire growth. Further, electrochemical wet etching processes require very low resistivity in the silicon substrates, e.g., <0.01 Ωcm, which limits process applications.
Kleimann et al., Toward the formation of three-dimensional nanostructures by electrochemical etching of silicon, Appl. Phys. Lett. 86, 183108-1-183108-3 (2005) describe lithographic etching techniques.
Schubert et al., Silicon nanowhiskers grown on (111)Si substrates by molecular-beam epitaxy, Appl. Phys. Left. Vol. 84, No. 24, pp 4968-4970 (2004) describe use of gold seeds to grow silicon nanowhiskers.
A method of fabricating silicon nanostructures includes preparing a silicon wafer as a substrate; forming an oxide layer hardmask directly on the silicon substrate; patterning and etching the, oxide hardmask; wet etching the silicon wafer to remove oxide to reduce the size of the oxide hardmask and to form nanostructure elements; and dry etching, in one or more steps, the silicon wafer using the oxide hardmask to form a desired nanostructure having substantially parallel vertical sidewalls thereon.
It is an object of the invention to provide a method of precisely fabricating nanostructures on a silicon wafer.
It is another object of the invention to provide a method of precisely fabricating nanostructures having substantially parallel vertical surfaces.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.
A low-cost technique to form various kinds of three-dimensional (3D) structures in silicon from nanosized to submicrometer scale, e.g., 50 nm-1000 nm, is disclosed. There is no physical limitation in application of the method of the invention below 50 nm, as in the above-cited, known prior art. An etching process, which combines conventional dry and conventional wet etching, using a hardmask, such as SiO2, or other oxide materials, such as ZrO2, HfO2, Al2O3, TiO2, Ta2O5, Nb2O5, Y2O3, La2O3, etc., to fabricate precise size-controlled silicon nanostructures, including nanorods, nanowires, nanotips and nanotubes is described to exemplify the method of the invention. Using these processes, it is easy to control nanostructure position, distribution and orientation by lithography and substrate orientation. The processes have no special resistivity requirement for the silicon wafers, and also fit within conventional semiconductor processes.
The method of the invention includes provision of an oxide hardmask and two, or more, dry etching steps, combined with a wet etching process, for making silicon nanostructure substrates. Silicon nanostructures having diameters ranging from nanosize to submicrometer scale, e.g., 50 nm to 1000 nm in diameter and 1 μm to 3+μm in height are obtained.
Referring now to
The oxide layer is covered with photoresist, pattered and etched, 16. Again, the patterning depends on requirements of the nanowire diameter. The oxide layer is etched, stopping at the level of the silicon substrate. The oxide may be further HF wet etched, following application of photoresist and patterning, to further reduce the hardmask size if there is a limitation of the lithography system. The photoresist is then removed.
If oxide materials other than SiO2 are used, the wafer is fully oxidized, at a low temperature of between about 400° C. to 500° C., which does not significantly oxidize any exposed silicon surface. Any oxidized silicon may be removed by a quick HF wet etch, which will not affect the fully oxidized other metal oxide. The silicon substrate is wet etched 18 to form initial nanostructure elements.
The silicon substrate is now dry etched 20, using the oxide hardmask and two, or more, dry etching steps to configure the nanostructure elements into the desired nanostructure configuration. Further silicon oxidation and HF wet etching may be required to achieve the desired nanostructure size and height.
The wet etching and dry etching protocols are listed in the following Tables.
The etching rate of silicon is much higher than that of SiO2 and other metal oxides when using the silicon dry etching protocols of Tables 4 and 5, thus, a SiO2, or other metal oxide layer, may be used as a hardmask for silicon nanostructure etching. Silicon nanostructures having diameters from nanosize to submicrometer, e.g., 50 nm-1000 nm (diameter)×1 μm to 3+μm (height) are obtained. Utilization of thermal oxidation and oxide etching processes can produce thinner silicon nanowires.
A silicon wafer, e.g., Si (111) is prepared. A layer of SiO2, having a thickness of about 500 nm, is formed directly on the silicon wafer, using a thermal oxidation process. The oxide layer is coated with photoresist, patterned with appropriate diameter×distance of between about 0.8 μm×1.6 μm. The oxide is etched to form nanostructure elements using the protocol of Table 6, and the photoresist then removed. Initially, the nanostructure elements have a somewhat pyramidal form.
The silicon is dry etched using the oxide hardmask and the protocol of Table 7.
The wafer is cleaned with HF, 50:1 for 40 minutes, to remove the SiO2 hardmask. The resultant wafer has the desired nanostructure configuration of silicon microrods thereon, having a 0.8 μm (diameter)×0.5 μm (height)×1.6 μm (distance), and are depicted in the microphotograph of
A silicon wafer is prepared. The wafer is coated with photoresist and patterned to provide a mask which result in a nanostructure having a diameter×distance of 0.8 μm×1.6 μm. The silicon of the wafer is dry etched using the protocol of Table 8.
Following the etching, the photoresist is removed, and the wafer cleaned in HF 50:1 for 5 minutes to remove any surface SiO2. Silicon microrods having a 0.5 μm (diameter)×2 μm (height)×1.6 μm (distance) are formed, as shown in
A silicon (111) wafer is prepared. A layer of SiO2, having a thickness of about 500 nm is formed on the silicon wafers using a thermal oxidation process. The oxide layer is coated with photoresist, and patterned to produce nanostructures having a diameter×distance ranges of 0.8 μm×1.6 μm and 1.5 μm×2 μm. The oxide layer is etched, stopping at the level of the silicon substrate, using Table 6 protocols. The photoresist is removed. The silicon wafer is dry etched using Table 7 protocols in the first step and Table 8 protocols in the second step.
The wafer is cleaned in HF 50:1 for 40 minutes to remove the SiO2 hardmask. The resulting wafer has silicon microtips having diameters of between about 0.8 μm to 1.5 μm, a height of about 3 μm, and spacing of about 2 μm, as shown in
The silicon is further oxidized to an oxide thickness of about 200 nm by thermal oxidation and HF 50:1 wet etching for 40 minutes, resulting in silicon microtips having a range of between about 0.5 μm to 1 μm(diameter)×3 μm (height)×2 μm (distance), as shown in
A silicon (110) wafer is prepared. A layer of SiO2, having a thickness of about 500 nm is formed on the silicon wafers using a thermal oxidation process. The oxide is coated with photoresist and patterned to provide for nanostructures having a diameter×distance of 0.8 μm×1.6 μm. The patterned oxide is etched using Table 6 protocols, stopping at the level of the silicon wafer. The silicon wafer is dry etched using Table 8 protocols in the first step and Table 7 protocols in the second step. The wafer is cleaned in HF 50:1 for 40 minutes to remove the SiO2 hardmask. The resultant silicon microtips have a 0.8 μm (diameter)×2 μm (height)×1.6 μm (distance), as shown in
A silicon (100) wafer is prepared. A layer of SiO2 is formed directly on the silicon wafer to a thickness of about 500 nm using a thermal oxidation process. The oxide layer is coated with photoresist, and patterned to produce a resultant nanostructure having a diameter×distance of 0.8 μm×1.6 μm. The oxide is etched, using Table 6 protocols, stopping at the level of the silicon substrate. The wafer is cleaned in HF 50:1 wet etching oxide for 20 minutes. The photoresist is removed. The wafer is then dry etched, using Table 8 protocols.
The wafer is again cleaned in HF 50:1 for 40 minutes to remove the SiO2 hardmask, resulting in silicon microwires having a mixture of diameters of between about 0.2 μm to 0.3 μm×1 μm (height)×1.6 μm (distance), as shown in
A silicon (111) wafer is prepared. A layer of SiO2 having a thickness of about 500 nm is formed directly on the silicon wafer using a thermal oxidation process. The oxide is coated with photoresist and patterned to provide a nanostructure having a diameter×distance of 0.8 μm×1.6 μm. The oxide is etched, using Table 6 protocols, stopping at the level of the silicon wafer. The photoresist is removed. The silicon is dry etched using Table 8 protocols in the first step and Table 7 protocols in the second step. The resultant silicon microrods have a size of 0.8 μm (diameter)×3 μm (height)×1.6 μm (distance), as shown in
Etching of the silicon continues using Table 8 protocols. The wafer is cleaned in HF 50:1 for 80 minutes to remove the SiO2 hardmask, producing silicon microwire having a 50 nm to 100 nm (diameter)×3 μm (height)×1.6 μm (distance), as shown in
Thus, a low-cost technique to form various kinds of three-dimensional (3D) structures in silicon from nanosized to submicrometer scale (50 nm to 1000 nm) has been disclosed. It will be appreciated that further variations and modifications thereof may be made within the scope of the invention as defined in the appended claims.
