The present invention relates generally to a silicon on insulator (SOI) device, and more specifically to a silicon on insulator (SOI) device applying trapping layers or implanting negative charges.
Integrated circuits are formed on semiconductor substrates and are packaged to form so-called chips or micro-chips. Traditionally, integrated circuits are formed on bulk semiconductor substrates comprising semiconductor material, such as silicon. In more recent years, semiconductor-on-insulator (SOI) substrates have emerged as an alternative. SOI substrate has a thin layer of active semiconductor separated from an underlying handle substrate by a layer of insulating material. The layer of insulating material electrically isolates the thin layer of active semiconductor from the handle substrate, thereby reducing current leakage of devices formed within the thin layer of active semiconductor. The thin layer of active semiconductor provides advantages. One advantage is dramatic decrease in parasitic capacitance which allows access to a more desirable power-speed performance horizon. Thus, SOI devices are particularly widely used for high frequency devices.
The present invention provides a silicon on insulator (SOI) device, which forms negative carriers right next to an induced positive fixed charge layer, to wipe out positive charges, thereby interrupting parasitic surface conduction (PSC) channels and thus reducing substrate loss.
The present invention provides a silicon on insulator (SOI) device including a wafer and a trap-rich layer. The wafer includes a top silicon layer disposed on a buried oxide layer. The trap-rich layer having nano-dots and an oxide layer are stacked on a high resistivity substrate sequentially, wherein the oxide layer is bonded with the buried oxide layer.
The present invention provides a silicon on insulator (SOI) device including a wafer and a high resistivity substrate. The wafer includes a top silicon layer disposed on a buried oxide layer. The high resistivity substrate is bonded with the buried oxide layer, wherein a positive fixed charge layer is induced at a surface of the buried oxide layer contacting the high resistivity substrate, and a doped negative charge layer is right next to the positive fixed charge layer.
According to the above, the present invention provides a silicon on insulator (SOI) device, which forms negative carriers right next to an induced positive charge layer, to wipe out positive charges in the induced positive charge layer. In one embodiment, a trap-rich layer having nano-dots is applied to trap negative carriers and wipe out induced positive charges in a positive fixed charge layer induced at a surface. In another embodiment, a doped negative charge layer including negative carriers therein is applied instead, to wipe out the positive charges. Thus, interrupt parasitic surface conduction (PSC) channels, increase effective resistivity in substrates, and reduce harmonic distortion and substrate loss.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Then, the bottom silicon substrate 130 is removed to expose the buried oxide layer 120, as shown in
Moreover, as shown in
As shown in
As shown in
More precisely, the negative carriers 222e are trapped in dangling bonds of the nano-dots 222 in the trap-rich layer 220, which is formed right next to the surface S1 (interface) of the buried oxide layer 120 contacting the oxide layer 230, so that the negative carriers 222e can wipe out induced positive charges of the positive fixed charge layer C1 effectively.
Furthermore, the temporary substrate 140 maybe removed after the oxide layer 230 of
As shown in
To summarize, the present invention provides a silicon on insulator (SOI) device and forming method thereof, which forms negative carriers right next to an induced positive charge layer, to wipe out positive charges in the induced positive charge layer. In one embodiment, a wafer including a top silicon layer disposed on a buried oxide layer is provided, a trap-rich layer having nano-dots and an oxide layer are stacked on a high resistivity substrate sequentially, and then the oxide layer is bonded with the buried oxide layer. By doing this, negative carriers trapped in dangling bonds of the trap-rich layer wipe out positive charges of a positive fixed charge layer induced at a surface of the buried oxide layer contacting the oxide layer. In another embodiment, a wafer including a top silicon layer disposed on a buried oxide layer is provided, a high resistivity substrate is bonded with the buried oxide layer, and a doped negative charge layer is doped right next to a positive fixed charge layer induced at a surface of the buried oxide layer contacting the high resistivity substrate. By doing this, negative carriers of the doped negative charge layer wipe out positive charges of the positive fixed charge layer. By applying the present invention, parasitic surface conduction (PSC) channels in the substrate are canceled, effective resistivity of the substrate is increased, and harmonic distortion and substrate loss is reduced.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
This application is a division of U.S. application Ser. No. 17/079,552, filed on Oct. 26, 2020. The content of the application is incorporated herein by reference.
Number | Date | Country | |
---|---|---|---|
Parent | 17079552 | Oct 2020 | US |
Child | 18522119 | US |