Patent Application
20230243062
The present invention relates to a silicon wafer having a surface layer in which semiconductor devices are formed, and a method for producing the silicon wafer.
For the purpose of, e.g., reducing the leakage current of semiconductor devices such as transistors, semiconductor devices having, instead of a conventional planar structure, a three-dimensional structure of pillars, fins, etc. have been developed in recent years. An epitaxial wafer is generally used for such semiconductor devices which is obtained by slicing a silicon ingot grown by the Czochralski method, and which has a surface formed with an epitaxial layer of silicon.
However, as such a device structure is refined to the nano level, in the step of thermally oxidizing pillars, fins, etc. made of silicon to form gate oxide films on the surfaces, a silicon missing phenomenon is occurring frequently, in which silicon atoms are released from the pillars, the fins, etc. This silicon missing phenomenon causes the cores of the pillars, the fins, etc. to become thin and collapse, or causes the interfaces between the cores and the gate oxide films to become uneven, thereby increasing electrical resistance.
The inventors of the present application reached, from experimental results which they have obtained so far, the conclusion that, as disclosed, for example, in the below-identified Patent Document 1, the higher the oxygen concentration near the surface of the wafer, the higher the effect of reducing the silicon missing phenomenon, and they tried to increase the oxygen concentration in the surface by using a polished wafer instead of an epitaxial wafer, which is low in oxygen concentration in its surface layer. As a means for increasing the oxygen concentration in the surface of the wafer, as disclosed, for example, in the below-identified Patent Document 2, a method is known with which interstitial oxygen atoms are introduced into the surface layer of the wafer by a rapid thermal process in an oxygen-containing atmosphere.
Patent Document 1: PCT International Publication No. WO2019/017326
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2013-143504
In Patent Document 1, by using a wafer having, among general wafers, a relatively high oxygen concentration in its surface layer, specifically, about 1×1018/cm3, it is possible to reduce the silicon missing phenomenon to a certain extent, but there is still room for improvement. According to the method of Patent Document 2, while, by inward diffusion of oxygen from the wafer surface, an oxygen concentration peak forms at a predetermined depth from the surface, in the vicinity of the surface, a region having a relatively low oxygen concentration is formed by outward diffusion of oxygen during temperature ramp-down. Since semiconductor devices are generally formed in the surface layer of the wafer, there is still a problem in that, due to the silicon missing phenomenon affected by outward diffusion of oxygen, devices having a three-dimensional structure cannot be formed suitably.
It is an object of the present invention to provide a silicon wafer suitable for forming semiconductor devices having a minute three-dimensional structure, and a method for producing the silicon wafer.
In order to achieve the above object, the present invention provides a silicon wafer comprising a Czochralski wafer formed of silicon, the Czochralski wafer including: a bulk layer having an oxygen concentration of 0.5×1018/cm3 or more; and a surface layer extending from a surface of the wafer to 300 nm in depth, and having an oxygen concentration of 2×1018/cm3 or more.
By setting the oxygen concentration in the bulk layer within the above range, the interstitial oxygen prevents a slip dislocation during wafer production and device formation. Moreover, by setting the oxygen concentration in the surface layer within the above range, it is possible to effectively reduce the silicon missing phenomenon, and prevent, e.g., collapse of pillars, fins, etc.
In the silicon wafer, the surface layer from the surface to 300 nm in depth preferably has an oxygen concentration of 2.5×1018/cm3 or more.
By setting the oxygen concentration in the surface layer within the above range, it is possible to further increase the effect of reducing the silicon missing phenomenon.
For the silicon wafer, it is preferable that in a region of the wafer from the surface to 30 μm in depth, the density of void defects having a size of 15 nm or more is 1×106/cm3 or less, and the density of oxygen precipitates having an equivalent spherical diameter of 15 nm or more is 1×106/cm3 or less.
If the density of void defects having the above size or more is within the above range, the breakdown characteristics of gate oxide films on fins, pillars, etc. constituting three-dimensional structures are not reduced by the void defects. Moreover, by setting the density of oxygen precipitates having the above diameter or more within the above range, it is possible to prevent local deformation of the wafer due to the slip dislocation from the oxygen precipitates, and thus to prevent a reduction in the shape accuracy of the three-dimensional structures.
For the silicon wafer, in a region of the wafer from 100 μm in depth to a thickness center of the wafer, a vacancy concentration is preferably 1×1012/cm3 or more.
If the vacancy concentration is within the above range, oxygen precipitates are formed in the region of the above depth during device production. Since oxygen precipitates have a gettering effect of metallic impurities, the electric properties in the device forming region improve.
In the silicon wafer, a concentration difference Cv-C1 between a vacancy concentration Cv and an interstitial silicon atom concentration C1 in the single-crystal silicon is preferably within a range of −2.0×10 12/cm3 or more and 6.0×1012/cm3 or less.
A negative value of the concentration difference Cv-C1 means that the interstitial silicon atoms remain dominantly, and a positive value thereof means that the vacancies remain dominantly. By limiting the concentration difference Cv-C1 within the above range, i.e., by using a silicon wafer including a region generally called a defect-free region, it is possible to prevent the grown-in defects introduced during growth of silicon single crystals from remaining in the region of the wafer right under the wafer surface where the interstitial oxygen concentration is supersaturated. It is possible to adjust the value of the concentration difference Cv-C1 by controlling the ratio V/G, where V is the pull-up rate of the silicon single crystals, and G is the temperature gradient near the solid-liquid interface (within the temperature range from the melting point of silicon to about 1350° C.).
Also, the present invention provides a production method for producing a silicon wafer including a surface layer, and obtained by slicing an ingot of single-crystal silicon grown by a Czochralski method, the production method comprising: in an oxidizing atmosphere, keeping the silicon wafer for 5 seconds or more and 30 seconds or less at a maximum temperature within a range of 1315° C. or more and 1375° C. or less, and then cooling the silicon wafer from the maximum temperature to 1100° C. at a cooling rate of not less than 50° C./second and not more than 150° C./second; and after the cooling of the silicon wafer, removing the surface layer to a depth where an oxygen concentration is 2×1018/cm3 or more.
By keeping the wafer for a predetermined time within the above temperature range, it is possible to introduce supersaturated interstitial oxygen (2×1018/cm3 or more) which can effectively prevent the silicon missing phenomenon in the three-dimensional structures of pillars, fins, etc. Also, by cooling the wafer at a cooling rate within the above cooling range, it is possible to minimize outward diffusion of the interstitial oxygen during cooling. Also, by removing a portion of the surface layer to the above depth, it is possible to expose a high-oxygen region in the device formation region of the surface, and thus to ensure that the silicon missing phenomenon is reduced.
For the production method, the maximum temperature is preferably within a range of 1325° C. or more and 1350° C. or less.
By keeping the wafer within the above temperature range, it is possible to reliably introduce supersaturated interstitial oxygen which can effectively prevent the silicon missing phenomenon while reducing the slip resulting from heat stress.
For the production method, the oxidizing atmosphere is preferably an oxygen atmosphere of which the oxygen partial pressure is within a range of 1% or more and 100% or less.
By setting the oxygen partial pressure within the above range, it is possible to effectively introduce interstitial oxygen into the silicon wafer.
The production method preferably further comprises subjecting the wafer to heat treatment within a range of 1 hour or more and 4 hours or less and within a range of 800° C. or more and 1000° C. or less such that in a region of the wafer from 100 pm in depth to a thickness center of the wafer, oxygen precipitates having an equivalent spherical diameter of 15 nm or more are formed at a density of 1×108/cm3 or more.
By heat-treating the wafer within the range of the above temperature and the range of the above time, it is possible to reliably introduce, into the wafer, oxygen precipitates having the above diameter and formed at the above density, thereby ensuring a gettering effect of metallic impurities.
For the production method, vacancies are preferably introduced by the thermal process in an oxidizing atmosphere such that a vacancy concentration is 1×1012/cm3 or more in the region of the wafer from 100 μm in depth to the thickness center.
If the vacancy concentration is within the above range, as described above, oxygen precipitates are formed in the above depth region during device production, and the electric properties in the device formation region improve due to the gettering effect of metallic impurities by the oxygen precipitates.
The production method preferably further comprises introducing vacancies and interstitial silicon atoms such that a concentration difference Cv-C1 between a vacancy concentration Cv and an interstitial silicon atom concentration C1 in the single-crystal silicon is within a range of −2.0×1012/cm3 or more and 6.0×1012/cm3 or less.
By limiting, to −2.0×1012/cm3 or more and 6.0×1012/cm3 or less, the range of the concentration difference Cv-C1 between the vacancies and the interstitial silicon in the single-crystal silicon, as described above, it is possible to prevent the grown-in defects introduced during growth of silicon single crystals from remaining in the region of the wafer right under the wafer surface where the interstitial oxygen concentration is supersaturated.
The present invention provides a silicon wafer suitable for forming semiconductor devices having a minute three-dimensional structure; and a method for producing the silicon wafer.
This Czochralski wafer is obtained by slicing a silicon ingot grown by the Czochralski method, and is subjected to a predetermined heat treatment for surface modification. This silicon ingot contains, in the crystals, oxygen, as interstitial oxygen, eluted from a quartz crucible used during growth. While this interstitial oxygen is partially diffused outward from the wafter surface by the above heat treatment, a predetermined amount of interstitial oxygen remains in the surface layer 2. That interstitial oxygen is present in the surface layer 2 of the wafer 1 makes a difference from an epitaxial wafer, in which silicon is epitaxially grown on the surface of a Czochralski wafer by chemical vapor deposition (CVD), and interstitial oxygen is hardly present in the surface layer.
The surface layer 2 is a device forming region, in which three-dimensional structures are formed. That is, devices are formed in the region of the wafer 1 from the surface to 300 nm in depth. The interstitial oxygen concentration in the surface layer 2 is 2×1018/cm3 or more, and preferably 2.5×1018/cm3 or more. As described later, this interstitial oxygen is introduced by a rapid thermal process in an oxygen atmosphere. The higher this oxygen concentration, the higher the effect of reducing the silicon missing phenomenon while forming the three-dimensional structures, but by setting this concentration to 2×1018/cm3 or more, it is possible to obtain a predetermined reducing effect to such an extent that device formation is not adversely affected. This interstitial oxygen concentration can be increased up to 4×1018/cm3, which is the upper limit of the equilibrium concentration (solid solubility) of oxygen in the silicon.
The bulk layer 3 is located in a region of the wafer 1 deeper than the surface layer 2 in the thickness direction of the wafer 1, i.e., a region of the wafer 1 deeper than 300 nm in depth. The interstitial oxygen concentration in the bulk layer 3 is 0.5×1018/cm3 or more. The higher this oxygen concentration, the higher the effect of fixing the slip dislocation generated during heat treatment for wafer production or during heat treatment for device formation, but by setting this concentration to 0.5×1018/cm3 or more, it is possible to obtain a predetermined fixing effect to such an extent that the wafer 1 is not locally deformed. On the other hand, the interstitial oxygen concentration in the bulk layer 3 is preferably 1.5×1018/cm3 or less. By limiting the interstitial oxygen concentration within the above range, it is possible to reduce abnormal appearance of oxygen precipitates near the interface between the surface layer 2 and the bulk layer 3, and to prevent problems relating to the device properties such as a latch-up phenomenon.
In the region of the wafer 1 from the surface to 30 μm in depth, the density of void defects is 1×106/cm3 or less. The void defects are cavity defects caused by aggregation of vacancies introduced into the crystals during growth of a silicon ingot. If void defects are present in the device formation region, the breakdown characteristics of gate oxide films on the three-dimensional structures may deteriorate. In the step of keeping the wafer at a high temperature during the rapid thermal process in the wafer production, the void defects shrink to such an extent that the breakdown characteristics are not affected, or disappear, but the void defects may partially remain in the crystals. By setting the density of the void defects after the rapid thermal process within the above range, it is possible to minimize the influence of the void defects on the breakdown characteristics. The sizes of void defects controlled to the above density can be appropriately set, for example, to not less than 5 nm or not less than 10 nm, but they are particularly preferably set to 15 nm or more.
In the region of the wafer 1 from the surface to 30 μm in depth, the density of oxygen precipitates is 1×106/cm3 or less. While oxygen precipitates present in a deep region of the bulk layer 3 (e.g., at the depth of several tens of micrometers or more) will effectively act as gettering sources of metallic impurities, oxygen precipitates present near the surface layer 2 could become slip dislocation starting points, thereby adversely affecting the shape accuracy of the three-dimensional structures. By setting the density of the oxygen precipitates after the rapid thermal process, it is possible to minimize the influence of the oxygen precipitates on the shape accuracy. For the sizes of the oxygen precipitates controlled to the above density, the equivalent spherical diameters of the oxygen precipitates can be appropriately set, for example, to not less than 5 nm or not less than 10 nm, but they are particularly preferably set to 15 nm or more.
Such oxygen precipitates not only have a spherical shape but also often have a plate shape. For example, if the oxygen precipitates have a square plate shape having an aspect ratio (thickness/diagonal length) of β=0.01, since, for example, the equivalent spherical diameter of 15 nm corresponds to a diagonal length of about 56 nm, the density of the plate-shaped oxygen precipitates having a diagonal length of about 56 nm or more is set to 1×106/cm3 or less.
In the region of the bulk layer 3 from 100 μm in depth to the thickness center of the wafer 1, the vacancy concentration is 1×1012/cm3 or more. It is considered that vacancies are present as complexes with interstitial oxygen (vacancy-oxygen complexes VOx). The vacancies (vacancy-oxygen complexes) promote formation of oxygen precipitates in the bulk layer 3 during device formation, and a high gettering effect of metallic impurities is ensured. By setting this vacancy concentration to 5×1012/cm3 or more, it is possible to ensure a higher gettering effect.
The silicon ingot from which the wafer 1 is formed is not particularly limited, but, in this embodiment, a silicon ingot is used in which the concentration difference Cv-C1 between the vacancy concentration Cv and the interstitial silicon atom concentration C1 is within the range of −2.0×1012/cm3 or more and 6.0×1012/cm3 or less (neutral region). By setting the concentration difference Cv-C1 within the above range, it is possible to easily produce a high-quality wafer 1 in which void defects are not introduced during growth of the crystals, or, even if void defects are introduced, their sizes are very small and no void defects are present in the device formation region due to the rapid thermal process.
Even though the concentration difference Cv-C1 is within the range of 1.3×1013/cm3 or more and 5.6×1012/cm3 or less (V-rich crystals) or within the range of 3.5×1012/cm3 or more and 1.1×1013/cm3 or less (Low COP crystals), it is still possible to make void defects disappear by appropriately changing the maximum temperature and the retention time of the rapid thermal process.
Next, a method for producing the wafer 1 of
While the wafer is kept at the maximum temperature during this rapid thermal process, oxide films are formed on the surface of the wafer 1, and supersaturated interstitial oxygen is introduced from the interface between each oxide film and the silicon. The interstitial oxygen diffuses inwardly toward the thickness center of the wafer 1. On the other hand, during cooling of the wafer 1, the interstitial oxygen diffuses outwardly toward the surface of the wafer 1, and the oxygen concentration near the surface decreases. As a result, as shown in
Next, the surface of the wafer 1 was removed by polishing to the depth where the oxygen concentration is 2×1018/cm3 or more. As a result, as shown in
In the above, for example, the distribution of the oxygen concentration during the thermal process was obtained by simulation (see
If an oxygen atmosphere is selected as the oxidizing atmosphere for the rapid thermal process, the oxygen partial pressure is preferably 100% in that interstitial oxygen can be efficiently introduced into the wafer 1, but can be set appropriately within the range of 1% or more and 100% or less. The oxidizing atmosphere is not limited to an oxygen atmosphere, and may be another atmosphere provided that interstitial oxygen can be introduced into the wafer 1.
After the rapid thermal process and then removing the surface, the wafer 1 was subjected to heat treatment at 800° C. for 1 hour in an argon atmosphere. By this heat treatment, oxygen precipitates having an equivalent spherical diameter of 15 nm or more are introduced, at a density of 1×108/cm3 or more, into the region of the wafer 1 from 100 μm in depth to the thickness center. By ensuring that such oxygen precipitates are introduced into the wafer in this way, it is possible to ensure the gettering effect of metallic impurities. It is known that formation of oxygen precipitates is promoted by the vacancies (vacancy-oxygen complexes) introduced into the wafer 1 by the rapid thermal process, and the region where oxygen precipitates form corresponds to the region where the vacancy concentration (vacancy-oxygen complex concentration) is 1×1012/cm3 or more.
The above heat treatment is preferably performed within the temperature range of not less than 800° C. and not more than 1000° C., and the time range of not less than 1 hour and not more than 4 hours, which hardly affect the vacancies (vacancy-oxygen complexes) introduced by the rapid thermal process.
The silicon ingot as the starting material in this method for producing the wafer 1 is not particularly limited, but, in this embodiment, a single-crystal silicon ingot is used which is grown by the Czochralski method, and in which the concentration difference Cv-C1 between the vacancy concentration Cv and the interstitial silicon atom concentration C1 is within the range of −2.0×1012/cm3 or more and 6.0×1012/cm3 or less (neutral region). By limiting the concentration difference Cv-C1 within the above range, it is possible to easily produce a high-quality wafer 1 in which no void defects are present in the device formation region due to a rapid thermal process.
The above-described wafer 1 and method for producing the wafer are mere examples, and a modification may be made thereto provided that the object of the present invention can be achieved, i.e., it is possible to provide a silicon wafer 1 suitable for formation of semiconductor devices having a minute three-dimensional structure, and a method for producing the silicon wafer 1.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2020-108627 | Jun 2020 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2021/022485 | 6/14/2021 | WO |
