Patent Application
20100136781
The present invention relates generally to semiconductor device fabrication and more particularly to the formation of back end of the line metal and via levels with a single photolithography mask.
Modern day integrated chips are comprised of a very large number of semiconductor devices having microscopic dimensions. Operation of the semiconductor devices comprised within an integrated chip depend upon a robust system of electrical connections between the semiconductor devices and the outside world. These electrical connections are formed by a complex configuration of metal interconnect levels (i.e., metal levels; metal wire levels) that electrically interconnect various semiconductor devices of an integrated chip to each other and to an external power supply.
The alternating metal and via levels typically increase in minimum horizontal dimension (e.g., metal line thickness) and vertical dimension (e.g., metal line height) as they appear vertically higher in the stack (e.g., thinner metal wire M1 is located below thicker metal wires M3 and M4). For example, as shown in
Metal wire levels and via levels are fabricated using separate lithography and etch steps. Using a dual damascene process, fabrication of the metal and via levels comprises forming a metal and via level within a deposited inter-level dielectric (ILD) material layer (e.g., silicon oxide, fluorinated silicon oxide, polymers including polyimide and fluorinated polyimide, ceramics, carbon and other dielectric materials). During processing, the ILD layer is deposited and then holes (i.e., via holes) are patterned using known techniques such as the use of a photoresist material which is exposed to define a pattern. After developing, the photoresist acts as a mask through which the pattern of the ILD material is removed by a subtractive etch process (e.g., such as plasma etching or reactive ion etching) to partially form the via holes. A second patterning process proceeds to pattern metal wires within the ILD layer. The pattern is also removed through a subtractive etch process which forms metal trenches and completes via hole etching such that the via holes extend from top surface of the ILD layer to the bottom surface of the ILD layer, while the metal trenches are comprised within the upper part of the ILD layer. The via holes and metal trenches are then filled a single metal deposition step to form both a via level and a vertically abutting metal layer (e.g., the metal layer above the via). Metal may be deposited using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination of methods. This process may further include planarization of the metal by removing excess material with a method such as chemical mechanical polishing.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary presents one or more concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later and is not an extensive overview of the invention. In this regard, the summary is not intended to identify key or critical elements of the invention, nor does the summary delineate the scope of the invention.
One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level within a single inter-level dielectric layer utilizing a single lithographic process (e.g., exposure) and a single etch step by utilizing an interdependence between the critical dimension of a feature (e.g., metal structure width) and the thickness to which it will form in a deposited ILD layer (e.g., metal structure height). In other words, a metal and via level are formed by a single lithography and etch step by utilizing an interdependence between a features critical dimension and ILD etch rate for that feature.
More particularly, a photolithography mask comprising a mask via shape and one or more mask wire shapes is configured to produce both on-wafer metal wire and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively abutting the on-wafer via opening and respectively having a second critical dimension (CD). The first critical dimension is larger than the second critical dimension thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in critical dimension subsequently results in a via level and one or more metal wire levels, wherein the via level extends vertically below the one or more metal wire level (e.g., the via region's higher etch rate causes the via to extend through the ILD layer to a metal level below, while the metal wire regions slower etch rate causes the ILD layer to separate the one or more metal wires and the metal level below).
The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed.
The present invention will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale.
In the examples of this disclosure, the dimensions disclosed for via and metal line width, as well as any other pattern dimensions disclosed herein unless otherwise expressly stated, are based upon the size of the pattern to be formed on the wafer. The actual dimensions for via and metal line width for the photomask patterns will vary depending upon the size of the reduction factor of the photomask. Photomasks are often formed to have, for example, a 4× or 5× reduction factor, meaning that the photomask pattern dimensions can be about 4 or 5 times larger than the corresponding dimensions formed on the wafer. Similarly, the dimensions of the drawn pattern may or may not also have a reduction factor. Therefore, as one of ordinary skill in the art would readily understand, the mask sizes and the drawn pattern sizes can correspond to the wafer dimensions based on any suitable reduction factor, including where the dimensions on the mask and/or drawn pattern dimensions are intended to be the same as those formed on the wafer.
Over the course of its life, the semiconductor industry has relied upon a strategy of scaling down the feature size of integrated chip components to improve speed and functionality of integrated chips. For many years the industry continued to fabricate decreased design sizes through decreasing the wavelength of the illumination source used for lithography. In recent years however, tool vendors have been unable to decrease the wavelength of illuminations sources and developing technology nodes now have minimum feature sizes of 20% or less than the wavelength of illumination used in exposure tools. Therefore, successful lithographic exposure of emerging technology thin metal levels relies upon costly resolution enhancement techniques (e.g., immersion lithography, alternating phase shift masks, double patterning/exposure techniques, etc.) that have allowed continued scaling. Such techniques have made the fabrication of modern day integrated chips is an extremely complex and expensive process. Therefore, it would be advantageous to be able to form more than one design level using a single photolithography mask.
One embodiment of the present invention relates to a photolithography mask configured to form a metal wire level and a via level within a single inter-level dielectric (ILD) layer using a single level photolithography mask (mask), exposure step, and etch step. More particularly, the present invention relies upon the critical dimension of a feature (e.g., metal structure width) to form a greater etch rate where the via is to be formed compared to the etch rate where the one or more metal wires are to be formed, resulting in the formation of both vias and metal wires using a single processing step (e.g., lithography exposure and etch step). In other words, a metal and via level are formed by a single lithography and etch step by utilizing an interdependence between a features critical dimension and ILD etch rate for that feature's width.
Essentially, a photolithography mask comprising a mask via shape (i.e., via shape on a mask that allows illumination to pass through the mask) and one or more mask wire shapes (i.e., one or more wire shapes on a mask that allow illumination to pass through the mask) is configured to produce both on-wafer metal line and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively abutting the on-wafer via opening and respectively having a second critical dimension. The first critical dimension is sufficiently different (e.g., larger) than the second critical dimension to provide a variation in the vertical etch rate between ILD exposed by the opening of the one or more mask wire shapes and the mask via shape (e.g., to provide a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings). This difference in critical dimension subsequently results in a via level and metal level vertically extending to different heights. For example, one embodiment a mask via shape having a substantially larger critical dimension than the one or more mask wire shapes will result in a via level that extends vertically below the metal wire level (e.g., the via region's higher etch rate causes the via to extend through the ILD to the metal level below, while the metal wire regions slower etch rate causes ILD material to separate the metal wires and the metal level below).
As will be more fully appreciated below, the difference in critical dimension between the mask via shape and the one or more mask wire shapes is predetermined and configured to be sufficiently large such that the difference in vertical depth between the resultant via and metal wire levels is sufficient to prevent inter-level dielectric breakdown between the metal wire level and underlying metal wires. For example, a photolithographic mask provided herein to form a V1 and M2 metal level (e.g., see
The present invention relies upon a strong dependence between inter-level dielectric etch rates and critical dimension (e.g., width) of a feature.
It will be appreciated that although the figures of this disclosures will be described in relation to an etch process as illustrated in
Referring again to
Therefore, as illustrated in
While method 600 is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the disclosure herein. Also, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.
At 602 a photolithography mask is formed having both mask wire shapes and mask via shapes. More particularly, the mask comprises a mask via region and a mask wire region, wherein the mask via region is selectively chosen to define a pattern of a via hole in a photoresist having a first critical dimension, and wherein the mask wire region is selectively chosen to define a pattern of a metal wire trench in a photoresist having a second critical dimension substantially smaller than the first critical dimension (e.g., see
A semiconductor substrate is provided at 604. The substrate may comprise any type of semiconductor body (e.g., silicon, SiGe, SOI) such as a semiconductor wafer or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or otherwise associated therewith. The semiconductor substrate will comprise at least one conductive layer (e.g., a first metallization level connected to semiconductor devices).
At 606 an ILD layer material layer is formed on the semiconductor substrate. In general, ILD layers having low dielectric constants are used for thin metal layers. In one embodiment an ultra-low dielectric material is deposited onto the semiconductor substrate. In an alternative embodiment silicon oxycarbide (SiCO) is deposited as an ILD layer onto the semiconductor substrate.
At 608 a hard mask is optionally deposited onto the ILD layer. The hard mask 1002 may be, for example, around 50 to 500 nm thick and, for example, comprises TiAlN, TiN, Ti, TiO2, Al, AlOx, AlN, TiAl, TiAlOx, Ta, TaOx, TaN, Cr, CrN, CrOx, Zr, ZrOx, ZrN, Hf, HfN, HfOx, silicon-rich nitride (SRN), silicon-rich oxynitride (SRON), silicon oxide, low-k dielectric, or any stack or combination thereof. An example of a hard mask stack is 300 nm of PECVD deposited SiO2 on 50 nm of sputter deposited TiAlN or TiN.
The deposition of the hard mask 1002 may comprise a single or multi-layer stack of different materials in order to better control the hard mask profile and remaining hard mask thickness. For example, a hard mask stack is 30 nm of TiAlN on 120 nm of TiAl, which is formed on 20 nm TiAlO which is formed on 50 nm of TiAlN. All of these layers are, for example, deposited by sputter deposition in the same chamber where the film composition is changed during the deposition by varying the gas composition (Ar+N2 (50/50) for nitride, Ar for metal, and Ar+O2 (90/10) or Ar+N2+O2 (85/10/5) for oxide). The TiAlN is, for example, deposited at around 400 C with high power to achieve roughly 100 nm/min TiAlN deposition rate. The TiAlN can be replaced by TiN for all of these cases.
At 610 a photoresist layer is formed on the semiconductor substrate above the ILD layer. Photoresist is an illumination sensitive film used to pattern substrates by blocking the substrate from exposure to implant, etch, etc. Photoresist comes in two tones, positive and negative. Positive photoresist will be structurally weakened when it is exposed and negative photoresist will be structurally strengthened when it is exposed. Substrates are completely covered with photoresist and after exposure the structurally weaker area of the photoresist is removed from the substrate through etching leaving the more robust area on the substrate covered.
A lithographic process is performed using the photolithography mask provided herein at 612 and 614. The lithographic process comprises exposure of the photoresist layer (612) and removal (i.e., development) of the exposed photoresist layer (614). More particularly, an illumination source selectively exposes the photoresist 802 through a mask 902 placed between the illumination source 908 and the photoresist 802. The photoresist 802 is then developed resulting in the removal of exposed photoresist 910. This forms openings in the photoresist for both via holes and metal wire lines above the ILD layer (e.g., exposes the ILD layer at the location of the on-wafer vias and the on-wafer metal wires).
The optional hard mask is etched away at 616. The etchant used for hard mask 1002 etching may vary depending on the material used for the hard mask 1002. Reactive ion etching is often used for hard mask 1002 etching. For example, a titanium aluminum nitride (TiAlN) hard mask 1002 may be effectively etched using plasma made from a mixture of Cl2 and BCl3 in a cold substrate process or any other suitable etch process for etching TiAlN
The ILD level is etched away at 618. In one embodiment, shown in
Metal is deposited at 620. Metal is deposited into both the ILD via holes 1102 and metal trenches 1104 resulting in a via level 1202 and a metal level 1204 as shown in
In one particular embodiment, the photolithography mask shown in
The method and resulting structure formed by the photolithography mask provided herein has a number of advantages over prior art methods. For example, in emerging technology nodes vias are usually among the most difficult structure to form because the most difficult process for lithography is contact hole (i.e., via hole) imaging. Lithography k1 values for hole imaging have traditionally lagged behind that of line/space patterning. Furthermore, the two dimensional nature of the contact holes makes polarization ineffective when forming images from diffracted light, which images on the substrate with a high rate of incidence. This further widens the k1 gap between contact holes and line/space patterns such as polysilicon gates and metal interconnects. In recent technology nodes the most difficult lithography problem has been to image contact holes at minimum pitch. Random logic lines can be printed with a k1 value of 0.35-0.38. This value improves when using a single edge exposure to 0.4-0.42. Contact lithography k1 values lag well behind either of these. For example, considering a 50 nm contact on a 90 nm pitch using the latest lithography tools (where λ=193E-9 and NA=1.35) and Rayleigh's equation from the background section, the process will have a k1 value of 0.315. By printing vias (i.e., contacts holes) with a relatively large critical dimension the lithography resolution problems that often face contact hole imaging in emerging technologies are no longer relevant. Therefore, vias that are formed according to the mask and method provided herein will have a higher yield than traditional vias.
Furthermore, the large size of the large via region will improve reliability at via metal interfaces. Often manufacturing tolerances (e.g., critical dimension tolerance, overlay tolerance, etc.) make it difficult to align vias with a lower metal. This difficulty results in a reduced cross sectional intersection between vias and metal. Over time, a small shared surface between vias and metal can lead to electrical shorts due to electro-migration at the interface between the metal and the via. The large via size of the present invention reduces this problem by increasing via metal intersect area. The large via size is easily aligned to a small metal line therefore forming an intersect area that is substantially larger than that of a smaller via. This larger intersect area reduces electro-migration at the via/metal interface and accordingly improves reliability of the chip.
Moreover, the present invention provides significant cost savings in processing over prior art methods of forming a via and subsequent metal level. For example, the number of photolithography masks utilized for the formation of a via and metal level is reduced. This cost savings is significant at thin metal levels where highly complicated photolithography masks are extremely expensive. Therefore, in one particular embodiment of the present invention the photolithography mask provided herein is a thin metal level mask. Also, the elimination of processing steps reduces fabrication costs. For example, only one photolithography, one etch, and one surface prep step are needed for the formation of both the metal and via level as opposed to prior art methods which require separate photolithography, etch, and surface prep steps for the formation of each of the metal and via level (i.e., two photolithography, two etch, and two surface prep steps are needed for the formation of both the metal and via level).
Although the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.
