BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings in which:
FIG. 1 is perspective schematic view of a single-electron transistor in accordance with certain embodiments of the present invention;
FIG. 2 shows electron-beam micrographs of the single-electron transistor shown in FIG. 1;
FIG. 3 is a schematic plan view of a Hall bar including the single-electron transistor 1 shown in FIG. 1 and a test structure;
FIG. 4 shows plots of resistance against magnetic field for the test structure shown in FIG. 3;
FIGS. 5
a and 5b show plots of resistance against magnetic field for the single-electron transistor shown in FIG. 1;
FIGS. 6
a and 6b show plots of resistance against magnetic field orientation for different gate voltages for the single-electron transistor shown in FIG. 1;
FIG. 7 shows a plot of resistance against magnetic field orientation for the single-electron transistor shown in FIG. 1;
FIG. 8 shows a circuit model for a single-electron transistor;
FIG. 9 illustrates current-voltage plots for the single-electron transistor shown in FIG. 1;
Referring to FIGS. 10a and 10b show contributions to Gibbs energy associated with the transfer of charge from a lead to an island of a single-electron transistor;
FIG. 11 shows plots of density-dependent chemical potentials with respect to uniaxial anisotropy modelled using a k.p kinetic-exchange model;
FIG. 12 shows a plot of Coulomb blockade conductance as a function of gate voltage for the single-electron transistor shown in FIG. 1;
FIG. 13 shows a plot of resistance as a function of gate bias and magnetic field strength for the single-electron transistor shown in FIG. 1;
FIG. 14 shows plots of resistance against magnetic field for the single-electron transistor shown in FIG. 1;
FIGS. 15
a to 15c illustrate steps in a process of fabricating of the single-electron transistor shown in FIG. 1;
FIG. 16 shows Coulomb blockade oscillation curves for the single-electron transistor shown in FIG. 1;
FIG. 17 show plots of resistance against magnetic field for the single-electron transistor shown in FIG. 1;
FIGS. 18
a to 18c show illustrative potential distributions and stable magnetization states for different magnetisations angles;
FIG. 19 illustrates electrical switching of states;
FIG. 20 is a greyscale plot of conductance as a function of magnetic field for the single-electron transistor shown in FIG. 1;
FIGS. 21
a and 21b are conductance plots as a function of magnetic field for the single-electron transistor shown in FIG. 1;
FIG. 22 show plots of conductance against gate bias for B=0 T, B=−0.1 T, B=−0.022 T and B=−0.035 T for the single-electron transistor shown in FIG. 1;
FIG. 23 illustrates a process for manipulating and storing information using the single-electron transistor shown in FIG. 1;
FIG. 24 is a state table;
FIG. 25 is a schematic diagram of a generic device in accordance with certain embodiments of the present invention;
FIG. 26 shows a lateral conduction device in accordance with certain embodiments of the present invention;
FIG. 27 is a cross-section of the device shown in FIG. 26 taken along the line A-A′;
FIG. 28 illustrates a vertical conduction device in accordance with certain embodiments of the present invention;
FIG. 29 shows self-assembled islands;
FIG. 30 illustrates shape anisotropy;
FIG. 31 illustrates stabilization of magnetization of a ferromagnetic region in an external field; and
FIG. 32 illustrates a head in accordance with certain embodiments of the present invention.
Patent Application
20070200156
