This invention is related to other inventions which the subject of separate patent applications filed thereon. See: U.S. patent application Ser. No. 09/629,682 entitled “A Single Crystal, Dual Wafer, Tunneling Sensor or Switch with Silicon on Insulator Substrate and a Method of Making Same” and U.S. patent application Ser. No. 09/629,680 entitled “A Single Crystal, Dual Wafer, Tunneling Sensor or Switch with Substrate Protrusion and a Method of Making Same” both of which applications have the same filing date as this application. The inventors named in this application are the inventors of the first embodiment disclosed herein with reference to FIGS. 1A-12B. However, subsequent improvements have been made which reflect what is believed to be the best modes for practicing the invention. As such, this application includes a disclosure of those improvements in the embodiments after FIG. 12B to ensure that the best mode requirements of 35 USC 111 first paragraph have been satisfied.
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Number | Date | Country |
---|---|---|
43 05 033 | Oct 1993 | DE |
0 619 495 | Oct 1994 | EP |
04-369418 | Dec 1992 | JP |
08-203417 | Aug 1996 | JP |
9710698 | Mar 1997 | WO |
Entry |
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