Patent Application
20200350328
The present invention relates to a single-gate multiple-time programming non-volatile memory, particularly to a single-gate multiple-time programming non-volatile memory and an operation method thereof, wherein the edge of the drain is used as a capacitor to control the floating gate.
The CMOS (Complementary Metal Oxide Semiconductor) process has been a normal fabrication method for ASIC (Application Specific Integrated Circuit). EEPROM (Electrically Erasable Programmable Read Only Memory), which features electric programmability and erasability and would not lose its memory after power is turned off, has been one of the popular non-volatile memories in the computer and information age.
A non-volatile memory is programmed via keeping charges to vary the gate voltage of the transistor thereof, or not keeping charges to preserve the gate voltage of the transistor. For a non-volatile memory, an erasion operation is to eliminate all the charges kept in the non-volatile memory and restore all the transistors to have the original gate voltages. In the conventional single-gate non-volatile memory, there are many kinds of control voltages and many memory elements. Therefore, the conventional non-volatile memory has larger area and higher fabrication cost.
To overcome the abovementioned problems, the present invention provides a single-gate multiple-time programming non-volatile memory and an operation method thereof, so as to greatly reduce the area of the single-gate non-volatile memory and improve the production value of the single-gate non-volatile memory.
A primary objective of the present invention is to provide a single-gate multiple-time programming non-volatile memory and an operation method thereof, wherein the source and the drain in the non-volatile memory have different widths. The edge of the drain can be served as a capacitor to control the floating gate. Thereby, the minimum control voltages and elements during writing are involved to reduce the whole area. Compared with a conventional single-gate programming non-volatile memory having high cost due to complicated control, the present invention can greatly reduce the control lines and cost of the non-volatile memory on account of simple operation and the least elements.
To achieve the abovementioned objectives, the present invention provides a single-gate multiple-time programming non-volatile memory, which comprises a P-type semiconductor substrate, a transistor and a capacitor structure, wherein the transistor and the capacitor structure are disposed in the P-type semiconductor substrate. The transistor comprises a first dielectric layer, a first conduction gate and two highly-conductive ion-doped regions, the first dielectric layer is disposed on the P-type semiconductor substrate, and the first conduction gate is stacked on the first dielectric layer, and the ion-doped regions are respectively disposed at two sides of the first conduction gate and the first dielectric layer to function as a source and a drain and disposed in the P-type semiconductor substrate, wherein the source and the drain have different widths. The edge of the drain is utilized to serve as a capacitor to form the capacitor structure and control a floating gate. A lightly-doped region is located between the drain and the floating gate, and the lightly-doped region and the ion-doped regions are doped with the same type of ions, jointly functioning as a single floating gate of the non-volatile memory.
In the present invention, the semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate having a P-type well, the transistor structure is an N-type transistor, and the ion-doped regions and the lightly-doped region are N-type ion-doped regions.
Besides, an operation method of the single-gate multiple-time programming non-volatile memory respectively applies a substrate voltage Vsub, a source voltage Vs and a drain voltage Vd to the P-type semiconductor substrate, the source and the drain, so as to perform a writing process or an erasing process.
In writing,
In erasing,
Below, the embodiments are described in detail in cooperation with the drawings to make easily understood the technical contents, characteristics and accomplishments of the present invention.
Refer to
The single-gate multiple-time programming non-volatile memory 100 comprises a P-type semiconductor substrate 130 or a semiconductor substrate with a P-type well. In
In the invention, the widths of the source 113 and the drain 114 are the side lengths along a horizontal axis direction (i.e. the direction parallel to the direction from the source 113 to the drain 114), as shown in
The single-gate multiple-time programming non-volatile memory 100 is a three-terminal structure. As shown in
In writing,
In erasing,
Furthermore, the ranges of “High Voltage”, “Medium Voltage” and “Low Voltage” proposed in the above bias conditions are specifically described. The “High Voltage” refers to subtract the threshold voltage Vt of the transistor from the breakdown voltage of the drain to the source. The “Medium Voltage” refers to half of the breakdown voltage of the drain to the source. The “Low Voltage” refers to one quarter of the breakdown voltage of the drain to the source.
The structure of
In conclusion, compared with a conventional single-gate programming non-volatile memory having high cost due to complicated control, the single-gate multiple-time programming non-volatile memory and the operation method thereof of the present invention can greatly reduce the lengths of control lines, areas and production cost of the non-volatile memory on account of simple operation and the least elements and the least control voltages.
The embodiments described above are only to exemplify the present invention but not to limit the scope of the present invention. Therefore, any equivalent modification or variation according to the shapes, structures, features, or spirit disclosed by the present invention is to be also included within the scope of the present invention.
