Patent Application
20180358258
Disclosed embodiments relate to semiconductor device fabrication and more specifically to Silicon-on-Insulator (SOI) processing for forming integrated circuits that include top-side-contact trenches for connection to the handle portion through the top-side of the chip and isolation trenches for electrical isolation between components on the chip.
SOI is a semiconductor technology that produces higher performing, lower power (dynamic) devices as compared to traditional bulk silicon-based technology. SOI substrates are used for a variety of applications including Micro-Electro-Mechanical Systems (MEMS), power devices, and complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs). The SOI wafer comprises a sandwich structure including a device layer (or active layer) on the top, a buried oxide (BOX) layer (dielectric typically being silicon oxide) in the middle, and a handle portion or ‘handle wafer’ (typically being bulk silicon) on the bottom. SOI wafers can be produced by using a SIMOX (Separation by IMplantation of Oxygen) process which uses a very high dose oxygen implant process followed by a high temperature anneal, or wafer bonding to achieve thinner and precise device layer and ensure the requirement of thickness uniformity and low defect density.
In high voltage SOI processes, the handle portion potential with respect to the circuit components in the device layer can have a profound effect on the performance and electrical characteristics of these components. For example, the breakdown voltage, drive current, safe operating area (SOA), and capacitance of a drain extended MOS transistor such as a laterally diffused MOSFET (LDMOS) transistor are typically functions of the handle portion potential. It is therefore generally important to have a well-defined potential in the handle portion in order to ensure proper IC functionality.
The handle portion is commonly tied to certain fixed potentials with respect to the device layer (e.g., lowest potential or ground) through the IC packaging. This can be inconvenient and in some situations it can be difficult to implement, especially in situations where the handle portion needs to be tied to some high voltage. In these cases a top-side-contact (TSC) trench that allows connection to the handle portion through the top-side of the die is therefore useful.
This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. This Summary is not intended to limit the claimed subject matter's scope.
Disclosed embodiments include SOI process flows that form both smaller area trenches (e.g., isolation trenches) and larger area trenches (TSC trenches) using a single masking step, which by reducing one masking level provides a significant IC cost reduction. A method of forming an IC comprises forming at least one hard mask layer on a device layer of a SOI substrate including the device layer on a top, BOX layer in a middle, and a handle portion on a bottom. A pattern is etched using masking comprising a patterned masking layer to simultaneously to form both larger area trenches and smaller area trenches etching through the hard mask layer, the device layer, and the BOX layer. A dielectric liner is formed for lining the larger area trenches and for lining the smaller area trenches. A deposited dielectric layer fills the smaller area trenches but only partially fills a portion of the larger area trenches.
The larger area trenches are bottom etched through the deposited dielectric layer to provide a top side contact to the handle portion. The handle portion is implanted at a bottom of the larger area trenches to form a handle contact, and the larger area trenches are filled with an electrically conductive layer (e.g., doped polysilicon) to form a top side ohmic contact to the handle contact.
Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:
Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.
Also, the terms “coupled to” or “couples with” (and the like) as used herein without further qualification are intended to describe either an indirect or direct electrical connection. Thus, if a first device “couples” to a second device, that connection can be through a direct electrical connection where there are only parasitics in the pathway, or through an indirect electrical connection via intervening items including other devices and connections. For indirect coupling, the intervening item generally does not modify the information of a signal but may adjust its current level, voltage level, and/or power level.
As noted above, disclosed embodiments include methods of forming SOI ICs including larger area trenches (e.g., TSC trenches) and smaller area trenches (e.g., isolation trenches) using single mask level method of forming both of these trench sizes. The single mask level can form both high aspect ratio (AR) isolation trenches (e.g., 3 to 15) and lower AR wider TSC trenches that ohmically contact the handle portion of the SOI IC die from the top side of the die so that the IC can be biased at a desired voltage without the need for a down bond.
In a typical embodiment the device layer 105c comprises silicon, the BOX layer 105b comprises silicon oxide, and the handle portion 105a comprises silicon. The device layer 105c can comprise a lower portion comprising single crystal silicon from the SOI substrate from an SOI wafer vendor and an upper portion comprising an epitaxial silicon layer. The device layer 105c can be from 1 μm to 10 μm thick, such as 3 μm to 6 μm thick, the BOX layer 105b can be from 1 μm to 4 μm thick, and the handle portion 105a can be from 100 μm to 1,000 μm (1 mm) thick. In one particular embodiment the top deposited silicon oxide layer 110 is Plasma enhanced chemical vapor deposition (PECVD) deposited and is 1 μm to 2 μm thick, the deposited silicon nitride layer 109 is LPVCD (or PECVD) deposited and is 0.1 μm to 0.4 thick, and the pad oxide 108 is 100 A to 300 A thick and is thermally grown.
A typical deposition pressure used for the SACVD deposition is from 300 torr to 700 torr. For depositing a SACVD silicon oxide the reagents can comprise Tetraethyl orthosilicate (TEOS) and O3 (ozone) in a temperature range from 500° C. to 560° C., with the deposited thickness range depending on the trench volume for the smaller area isolation trenches being filled, such as 0.9 μm to 4 μm thick in one embodiment. SACVD is capable of completely filling high AR trenches, such as isolation trenches having an AR from 3 to 15.
There is generally no masking layer used for this bottom etching so that the SACVD dielectric layer 114 is blanket etched resulting in the field regions of the SACVD dielectric layer 114 being thinned too as shown in
The dielectric layer 114 thickness range in the case of a SACVD dielectric after densifying and blanket bottom etching for an as-deposited SACVD dielectric layer thickness of 0.9 μm to 1.1 μm is less than 0.45 μm (=4.5 kA) on the field, thus providing more than a 50% total thickness reduction. The densification process generally results in 4% to 10% film shrinkage, while the bulk of the SACVD thickness decrease generally results from the earlier bottom etch process.
Although the process progression shown in
Although not shown, as well known in the art subsequent IC processing includes lithography, etching, thin film depositions and growth, diffusion, and ion implants for forming a desired pattern of transistors, resistors and capacitors. Metallization follows generally comprising a multi-level metallization stack, followed by forming a patterned passivation layer to expose the bond pads.
For simplicity the metal stack is shown as only a patterned metal 1 (M1) layer 230 connecting through filled (e.g., tungsten (W) filled) vias 233 that are through a pre-metal dielectric layer 234 to provide contact to features in or on the top surface of the device layer 105c. Not all needed contacts are shown, such as contacts to the respective gates. Typically, the metal stack will include 4 or more metal layers with an interlevel dielectric (ILD) layer having vias therein between the respective metal layers.
The transistors shown comprise a laterally diffused n-channel metal-oxide-semiconductor (NLDMOS) transistor 250, and a conventional n-channel MOS (NMOS) transistor 260. The field oxide is shown as a LOCOS oxide 275, but as noted above can also comprise STI. As used herein, an LDMOS device is synonymous with a diffused metal oxide semiconductor (DMOS) or drain extended MOS (DEMOS) device and can include both n-channel LDMOS (NLDMOS) and p-channel PLDMOS devices. In NLDMOS transistor 250, the drain 251 is laterally arranged to allow current to laterally flow, and an n-drift region is interposed between the channel and the drain to provide a high drain 251 to source 252 breakdown voltage (BV). The source 252 is in a p-body region 256 (sometimes called a DWELL region) formed within an n-body region 259 that has a p+ contact 257. LDMOS devices are thus generally designed to achieve higher BV while minimizing specific ON-resistance in order to reduce conduction power losses. NLDMOS transistor 250 also has a gate electrode 254 such as an n+ polysilicon gate that is on a gate dielectric layer 253.
NMOS transistor 260 includes a gate electrode 221 on a gate dielectric 222 along with a drain 223 and source 224 formed in a pwell 225. Spacers 227 are shown on the sidewalls of the gate stack of the NMOS transistor 260. There is also a p+ contact 229 shown to the pwell 225. The IC 200 can also include PMOS devices by generally changing the doping types relative to NMOS devices.
Although only one ISO ring 320 is shown in
Disclosed embodiments can be used to form SOI semiconductor die that may be integrated into a variety of assembly flows to form a variety of different devices and related products. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, Insulated Gate Bipolar Transistor (IGBT), CMOS, BiCMOS and MEMS.
Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.
