Patent Application
20180350732
Embodiments of the present disclosure generally relate to methods of processing substrates and substrates fabricated according to such methods. Specifically, embodiments of the present disclosure relate to substrates having small vias formed in polymer layers disposed on a substrate and methods of fabricating such small vias.
In the fabrication of modern electronic devices, the increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques of such high density devices. Generally, the fabrication of modern electronics involves substrate level packaging. Substrate level packaging generally includes creating vias and similar structures for providing internal and external device connectivity, for example input/output (I/O) connectivity. Creating vias typically involves the use of a polymer material having dielectric properties and stress buffering capabilities. However, the inventors have observed that as via sizes scale down, small polymer via openings cannot be reliably formed and maintained without compromising the dielectric properties of the polymer materials.
Thus, the inventors have developed improved techniques to fabricate polymer vias.
Embodiments of methods for creating a small via polymer opening on a substrate are provided herein. In some embodiments, a method of processing a substrate having a conductive layer includes: (a) depositing a polymer layer atop the substrate to cover an exposed conductive layer on the substrate; (b) curing the polymer layer; (c) forming a patterned masking layer atop the cured polymer layer; (d) etching an exposed portion of the polymer layer through the patterned masking layer to form a via through the polymer layer to a top surface of the conductive layer; and (e) removing the patterned masking layer.
In some embodiments, a method of processing a substrate having a conductive layer includes: (a) depositing a polymer layer atop the substrate; (b) curing the polymer layer; (c) depositing a hard mask layer atop the polymer layer; (d) forming a patterned masking layer atop the hard mask layer; (e) etching exposed portions of the hard mask layer through the patterned masking layer to a top surface of the polymer layer; (f) etching exposed portions of the polymer layer through the patterned masking layer and the hard mask layer to a top surface of the conductive layer to form a via through the polymer layer; and (g) removing the patterned masking layer.
In some embodiments, a substrate for a packaging application includes: a cured polymer layer disposed atop a substrate; a conductive layer disposed in the substrate adjacent to and beneath the polymer layer; and a via formed through the cured polymer layer to expose a portion of the conductive layer, wherein the via has a width or diameter of less than 5 microns.
Other and further embodiments of the present disclosure are described below.
Embodiments of the present disclosure, briefly summarized above and discussed in greater detail below, can be understood by reference to the illustrative embodiments of the disclosure depicted in the appended drawings. However, the appended drawings illustrate only typical embodiments of the disclosure and are therefore not to be considered limiting of scope, for the disclosure may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
Embodiments of methods for forming vias in a polymer layer on a substrate are provided herein. The methods described herein advantageously provide the creation, on a substrate, of a small-sized via (e.g., less than 5 microns in width, or from about 1 to about 5 microns in width) having substantially vertical sidewalls. Small vias as disclosed herein advantageously facilitate direct via-stacked-on-via designs that further improve the allowable I/O density. Thus, the methods described herein may advantageously be utilized in advanced substrate-level packaging and in fan-out substrate level packaging for via critical dimension (CD) scaling.
The method 100 is performed on a substrate, such as the substrate 202 depicted in
For example, the substrate 202 may include a number of metallization levels having one or more conductive layers, such as metal traces, or the like. One of these conductive layers 204 is shown in
For example, the conductive layer 204 may be part of a dielectric layer deposited atop the substrate 202. In some embodiments, the dielectric layer may a low-k dielectric material (e.g., a material having a dielectric constant less than silicon oxide, or less than about 3.9). Examples of suitable dielectric materials include silicon dioxide (SiO2), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, a spin-on organic polymeric dielectric, or a spin-on silicon based polymeric dielectric. When present, the dielectric may be deposited by using any suitable deposition method used for such materials in semiconductor manufacturing processes. The dielectric layer may be deposited to a thickness of, for example, about 100 to about 2,000 angstroms. The thickness of the first dielectric layer varies depending upon factors such as the technology node, the architecture design, the process flow scheme, or the like.
The method generally begins at 102, and as depicted in
Generally, in substrate packaging applications consistent with the embodiments of the present disclosure, the polymer layer 206 is provided to act as a dielectric with stress buffering properties. Accordingly, the polymer layer 206 has a combination of mechanical properties configured to ensure robust chip-package reliability (e.g., thermal cycling, drop test, etc.).
In some embodiments, the polymer layer 206 is blanket deposited (i.e. deposited atop the entire exposed surface of the conductive layer 204 to advantageously reduce or eliminate roughness at the interface of the substrate 202 and the conductive layer 204. The polymer layer 206 may be deposited to a thickness of, for example, about 3 microns to about 7 microns, for example, about 6.8 microns. The thickness of the polymer layer 206 can vary depending upon factors such as the technology node, the architecture design, the process flow scheme, or the like. The polymer layer 206 may be deposited using any suitable deposition method commonly used in substrate packaging processes.
Next at 104, the polymer layer 206 is cured. The polymer layer 206 is cured at temperatures that harden and improve the physical and chemical properties of the polymer layer 206. In some embodiments, the curing temperature of the polymer layer 206 may be significantly higher than the temperatures used in performing other processing steps of the method 100. In some embodiments, for example, where the polymer layer 206 comprises PI or PBO, the polymer layer 206 may be cured at a temperature from about 180° C. to about 350° C. In some embodiments, the polymer layer 206 is cured using convective heating. In some embodiments, microwave energy, for example, variable frequency microwave (VFM) energy maybe used to cure the polymer layer 206.
Typically, the resolution limit for negative-tone polymers, for example polymide (PI), is about 8 to about 10 microns. Moreover, the inventors have observed that a negative-tone polymer via (e.g., PI polymer via) opening typically exhibits abnormal shape and may not be properly opened to a resolution below about 8 microns. The typical resolution limit for a positive-tone polymer via, for example polybenzoxazole (PBO) is 5 microns. Thus, vias formed directly in these polymer layers by photo-patterning the polymer layer itself requires larger via sizes. The inventors have observed that forming vias having smaller dimensions would be advantageous in applications such as wafer level and/or fan-out wafer level packaging. In addition, the inventors believe that a reduced polymer via size is advantageous to reduce effective area needed for via formation, thus allowing for more connectivity. The inventors believe that the reduced effective area needed for via formation would be especially valuable for very high I/O connectivity applications, e.g., die partitioning of field programmable gate arrays (FPGA).
As such, next, at 106, a patterned masking layer 208 is formed atop the cured polymer layer 206 to facilitate etching a via into the polymer layer 206 (as depicted in
The patterned masking layer 208 may be formed according to any process suitable to form a masking layer capable of providing an adequate template for defining a pattern in the underlying layer. In some embodiments, the patterned masking layer 208 may be spin coated on the polymer layer 206. In some embodiments, the patterned masking layer 208 may be formed through an etch process, such as a plasma-based dry etching process. The patterned masking layer 208 may be any suitable masking material, such as a photoresist. In some embodiments, the patterned masking layer 208 is provided as a negative photoresist. In some embodiments, the patterned masking layer 208 is provided as a positive photoresist. In some embodiments, the patterned masking layer 208 is an oxygen-containing layer, for example, a silicon oxide (SiOx) layer or a silicon oxynitride (SiON) layer.
The thickness of the patterned masking layer 208 is more than, equal to or less than the thickness of the polymer layer 206. For example, in some embodiments, when the polymer layer 206 is deposited to a thickness of about 3 to about 7 microns, for example 6.8 microns, the masking layer may be deposited to a thickness of about 3 microns. The patterned masking layer 208 is deposited on the polymer layer 206 to ensure the formation of a sturdy small via, capable of withstanding other process steps, such as removal of portions of the patterned masking layer 208.
As depicted in
Next at 112, and as depicted in
Next at 114, as depicted in
The removal of the patterned masking layer 208 leaves behind the via 212 having a depth equal to the thickness of the polymer layer 206 and a width equal to the desired via width. The sidewalls of the via 212 are vertical or substantially vertical. For example, in some embodiments, the sidewalls of the via 212 may have a vertical angle profile of about 80 to 90 degrees. The bottom of the via 212 is an exposed portion of the conductive layer 204.
The method 300 begins at 302. At 302, and as depicted in
Next at 306, and as depicted in
In some embodiments, the hard mask layer 402 is formed from a metal, for example, titanium, copper, or tantalum. The metal can be deposited using any suitable method known in the art. In some embodiments, for example, where the polymer layer 206 has a thickness of about 3 microns to about 7 microns, the metal hard mask layer 402 is deposited to a thickness of about 100 to about 1000 angstroms.
Next at 308, and as depicted in
Next at 310, and as depicted in
Next at 312, and as depicted in
Next at 314, as depicted in
In embodiments, where the hard mask layer 402 is an inorganic material, the method 300 may end at 314 with the removal of the patterned masking layer 208. However, in embodiments where the hard mask layer is a metal, the method 300 includes a further process 316 to remove remaining portions of the hard mask layer 402. When provided as a metal, the hard mask layer 402 is removed to prevent the creation of an unwanted conductive path between the hard mask layer 402 and the conductive layer 204. In some embodiments, the metal is removed using a suitable wet etch process, for example, using H2O2, or the like.
The removal of the patterned masking layer 208, or alternatively of both the patterned masking layer 208 and the hard mask layer 402 leaves behind the via 408 having a depth equal to the thickness of the polymer layer 206 (e.g., about 6.8 microns) and a width equal to the desired via width (e.g., about 2 microns). The sidewalls of the via 408 are vertical or substantially vertical. For example, in some embodiments, the sidewalls of the via 212 may have a vertical angle profile of about 80 degrees and about 90 degrees, for example, about 89 degrees. The bottom of the via 212 is an exposed portion of the conductive layer 204.
Thus, methods of forming vias in polymer layers have been provided herein. The vias can advantageously have a smaller size than typically possible when photo-patterning the vias directly in the polymer layer. The opening created in the polymer layer with a dry plasma etch has better resolution (e.g., <=2 μm) with better control of via CD uniformity and profile angle, as the opening geometry is no longer dependent on polymer dielectric lithography properties. Methods in accordance with the present disclosure thus further advantageously open up the possibility to switch to cheaper and better, non-photo sensitive polymers to function as the polymer layer. Improved via resolution further provides improved I/O density and also allows for direct via-stacked-on-via designs that further improve the allowable I/O density.
While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof.
This application claims benefit of U.S. provisional patent application Ser. No. 62/514,000, filed Jun. 1, 2017, which is herein incorporated by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62514000 | Jun 2017 | US |
