Claims
- 1. A method of forming a semiconductor device comprising the steps of:
- (a) providing a single crystalline substrate having a substantially planar surface;
- (b) forming a first surface area in the single crystalline substrate, the first surface area being a semiconductor on insulator region having a perimeter;
- (c) depositing a thin polish stop layer;
- (d) depositing a sacrificial layer;
- (e) forming openings in the sacrificial layer, thereby exposing portions of the thin polish stop layer;
- (f) etching the openings to a top of a bulk substrate;
- (g) growing single crystalline semiconductor material at least to the level of the thin polish stop layer; and
- (h) polishing the single crystalline semiconductor material to the thin polish stop layer.
- 2. The method of claim 1, wherein the first surface area is formed by high energy implantation of a large dose of oxygen, and further comprising the step, after step (f) and before step (g) of:
- etching into the top of the bulk substrate to remove a transition region.
- 3. The method of claim 1, wherein the growing of the single crystalline semiconductor is done in a non-selective manner.
- 4. The method of claim 3, wherein the polishing of the single crystalline semiconductor material includes a first polish step to the sacrificial layer and a second polish step to the thin polish stop layer.
- 5. The method of claim 1, wherein the single crystalline semiconductor material is grown to the midpoint of the sacrificial layer.
- 6. The method of claim 1, further comprising, after step (f) and before step (g), the step of:
- selectively forming a first spacer at a first portion of the perimeter of the semiconductor on insulator region.
- 7. The method of claim 6, wherein the spacer material is selected from the group consisting of:
- A conductive spacer material; insulative spacer material; and a conductive spacer material having an insulative spacer material on an upper surface thereof.
- 8. The method of claim 7, further comprising, after the formation of a spacer at a first portion of the perimeter, the step of:
- selectively forming a second spacer at a second portion of the perimeter.
Parent Case Info
This application is a divisional of application Ser. No. 08/878,225, now U.S. Pat. No. 5,894,152.
US Referenced Citations (7)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0 610 599A1 |
Dec 1993 |
EPX |
63-58817 |
Mar 1988 |
JPX |
64-12543 |
Jan 1989 |
JPX |
Non-Patent Literature Citations (3)
Entry |
IBM/Selective SOI and Integration With Planar Oxide-Isolated Bulk Devices/vol. 35 No. 5 Oct. 1992. |
SOI/Bulk Hybrid Technology on SIMOX Wafers for High Performance Circuits With Good ESD Immunity/Manuscript/1995. |
Proceedings 1996 IEEEE International SOI Conference, Oct. 1996/Floating-Body Concerns for SOI Dynamic Random Access Memory. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
878225 |
Jun 1997 |
|