This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2005-257085, filed on Sep. 5, 2005, and the prior Japanese Patent Application No. 2006-195075, filed on Jul. 18, 2006; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a solid-state imaging device and a method of manufacturing the same.
2. Background Art
Recently, in solid-state imaging devices such as CMOS image sensors, the pixel size has been significantly reduced to meet the demands for downsizing the device and increasing the number of pixels. A solid-state imaging device of today has a structure in which color filters, microlenses, and interconnects such as vertical signal lines are formed on photodiodes.
However, as the pixel size becomes even smaller and the interconnects are further multilayered, the distance from the sensor surface to the photodiodes is increased in the structure as described above, and obliquely incident light will suffer interference from the interconnects (shading effect). This prevents the light from reaching the photodiode and decreases the incidence efficiency of light incident on the photodiode.
In a disclosed technique (e.g., JP 2005-038908A), a gate electrode is buried in an element isolation layer between pixels. A signal charge stored in the N-type impurity region constituting the photodiode is transferred by this gate electrode to an N-type floating diffusion region formed on the N-type impurity region. However, even in this technique, it is difficult to solve the above-described problem because interconnects such as vertical signal lines are formed on the photodiodes.
According to an aspect of the invention, there is provided a solid-state imaging device comprising: a semiconductor substrate having; a first impurity region of a first conductivity type, the first impurity region storing a signal charge produced through photoelectric conversion by a photoelectric conversion section formed in a surface portion of the semiconductor substrate; a second impurity region of the first conductivity type formed below the first impurity region; and a first gate electrode penetrating the semiconductor substrate in a thickness direction of the semiconductor substrate, the first gate electrode transferring the signal charge stored in the first impurity region to the second impurity region; and a signal processing section provided on a backside of the semiconductor substrate, the signal processing section receiving the signal charge transferred to the second impurity region.
According to other aspect of the invention, there is provided a solid-state imaging device comprising: a semiconductor substrate having; a first impurity region of a first conductivity type, the first impurity region storing a signal charge produced through photoelectric conversion by a photoelectric conversion section formed in a surface portion of the semiconductor substrate; a second impurity region of the first conductivity type formed in the semiconductor substrate at a part lower than the first impurity region; a first gate electrode penetrating the semiconductor substrate in a thickness direction of the semiconductor substrate, the first gate electrode transferring the signal charge stored in the first impurity region to the second impurity region; and an overflow drain unit of the first conductivity type being in contact with the first impurity region, the overflow drain unit extending to a backside of the semiconductor substrate; and a signal processing section provided on the backside of the semiconductor substrate, the signal processing section receiving the signal charge transferred to the second impurity region.
According to other aspect of the invention, there is provided a method of manufacturing a solid-state imaging device, comprising: forming a first impurity region of a first conductivity type, the first impurity region storing a signal charge produced through photoelectric conversion by a photoelectric conversion section in a surface portion of a semiconductor substrate; forming a trench, the trench penetrating the semiconductor substrate; forming a second impurity region of the first conductivity type below the first impurity region in the semiconductor substrate by introducing impurities of the first conductivity type on at least one side face of an inner wall of the trench; forming a gate electrode by burying a conductive material in the trench via an insulating film; and forming a signal processing section on the backside of the semiconductor substrate.
Embodiments of the invention will now be described with reference to the drawings. In the embodiments, by way of illustration, a CMOS image sensor is used as an example of the solid-state imaging device.
As shown in
Because of the multilayer structure as described above, the thickness of the semiconductor substrate 2 can be varied as appropriate on the order of several micrometers to several hundreds of micrometers depending on the thickness of the constituent layers.
The P-type Si substrate 3 and the P-type epitaxial layer 5 have an impurity concentration of about 1.0×1018/cm3, and the P+-type epitaxial layer 4 has an impurity concentration of about 1.0×1020/cm3. The total thickness of the P+-type epitaxial layer 4 and the P-type epitaxial layer 5 is about 5 to 10 μm.
The semiconductor substrate 2 has trenches 2a that penetrate the semiconductor substrate 2 in the thickness direction. The trench 2a has a width of about 0.8 μm.
A gate insulating film 6 is formed on the inner wall of the trench 2a, and a gate electrode (a first gate electrode) 7 is formed inside the gate insulating film 6. In response to application of voltage, the gate electrode 7 serves to read a signal charge, which has been stored in an N-type impurity region 9 described later, and to transfer the signal charge to a charge storage region 13 described later. That is, this portion constitutes a transfer transistor 8, where the source is the N-type impurity region (a first impurity region) 9, the gate is the gate electrode 7, and the drain is the charge storage region (a second impurity region) 13. Through a read control line 29 described later, a common voltage is applied to the gate electrodes 7 adjacent to each other in the width direction of the trench 2a (horizontally across page in
An N-type impurity region 9 is formed as a first impurity region on the P-type epitaxial layer 5, which is the surface layer of the semiconductor substrate 2. One of the side faces of the N-type impurity region 9 is adjacent to the gate electrode 7 via the gate insulating film 6. The P-type epitaxial layer 5 and the N-type impurity region 9 constitute a photodiode 10, which is a photoelectric conversion section for converting incident light into a signal charge. The signal charge produced by photoelectric conversion is stored in the N-type impurity region 9.
The one side portion of the N-type impurity region 9 adjacent to the gate electrode 7 is formed deeper than the other portion of the N-type impurity region 9. The bottom of this side portion is adjacent to the P+-type epitaxial layer 4. The other side face of the N-type impurity region 9 is adjacent to a channel stopper region (an eighth impurity region) 11, which is provided for device isolation between the pixels P.
The channel stopper region 11 is a P+-type impurity region and formed in the upper portion of the P-type epitaxial layer 5, the P+-type epitaxial layer 4, and the P-type Si substrate 3. The side face of the channel stopper region 11 is adjacent to the gate insulating film 6 of the neighboring pixel P. That is, the channel stopper region 11 is juxtaposed with the gate insulating film 6 in the width direction of the trench 2a (horizontally across page in
As shown in
In
Below the N-type impurity region 9 and in the P-type Si substrate 3, a charge storage region 13 is formed as a second impurity region to which the signal charge stored in the N-type impurity region 9 is transferred. The charge storage region 13 is an N-type impurity region. One side face thereof is adjacent to the gate electrode 7 via the gate insulating film 6, and the upper face is adjacent to the P+-type epitaxial layer 4.
At the bottom of the P-type Si substrate 3 is formed a floating diffusion region (a sixth impurity region) 14 (this region is hereinafter referred to as “FD region”), which is a portion of a signal processing section 20 described later and to which the signal charge stored in the charge storage region 13 is transferred. The FD region 14 is an N-type impurity region. When the signal charge stored in the charge storage region 13 is transferred to the FD region 14, a voltage is applied to a gate electrode (a second gate electrode) 21a of a transfer transistor 21 described later.
On the frontside of the semiconductor substrate 2, a color filter 15 is formed. On the color filter 15 is formed a microlens 16, which serves as a lens for focusing light and guiding the light to the photodiode 10.
On the backside of the semiconductor substrate 2 (backside of the P-type Si substrate 3) is formed a signal processing section 20 to which the signal charge transferred to the charge storage region 13 is inputted. As shown in
The transfer transistor 21 transfers the signal charge stored in the charge storage region 13 to the FD region 14. The source of the transfer transistor 21 is the charge storage region 13, the gate is the gate electrode 21a, and the drain is the FD region 14. The gate electrode 21a is electrically connected to the read control line 30. On the other hand, the read control line 29 is electrically connected to the gate electrode 7 of the transfer transistor 8.
The reset transistor 22 periodically resets the signal charge stored in the FD region 14. The source, gate, and drain of the reset transistor 22 are electrically connected to the FD region 14, the reset control line 31, and the drain line 32, respectively.
The amplification transistor 23 detects voltage variation of the FD region 14 and converts it into a current signal. The drain, gate, and source of the amplification transistor 23 are electrically connected to the source of the vertical selection transistor 24, to the FD region 14, and to the vertical signal line 33, respectively.
The vertical selection transistor 24 and the horizontal selection transistor 25 serve to select a specific pixel column. The drain and gate of the vertical selection transistor 24 are electrically connected to the drain line 32 and the vertical selection control line 35, respectively. The drain, gate, and source of the horizontal selection transistor 25 are electrically connected to the vertical signal line 33, the horizontal selection control line 36, and the horizontal signal line 34, respectively.
Each pixel P includes a photodiode 10, transfer transistors 8 and 21, a reset transistor 22, an amplification transistor 23, and a vertical selection transistor 24.
The vertical scan circuit 26 applies voltage to the read control line 29 and the like to control the transfer transistor 8 and the like. The horizontal scan circuit 27 applies voltage to the horizontal selection control line 36 to control the horizontal selection transistor 25.
The CDS circuit 28 serves to remove fixed pattern noise due to the fluctuated threshold voltage of the transfer transistor 8 and the like included in the pixel P, and is interposed in the vertical signal line 33. The CDS circuit 28 is illustratively composed of two capacitors (not shown), a sampling transistor (not shown), and a clamp transistor (not shown).
The CMOS image sensor 1 is operated as follows. First, a voltage is applied to the vertical selection control line 35 by the vertical scan circuit 26, and the vertical selection transistor 24 is turned on. Thus a specific pixel column is selected.
Next, in this state, a voltage is applied to the read control line 29 by the vertical scan circuit 26, and the transfer transistor 8 is turned on. Thus the signal charge stored in the N-type impurity region 9 is transferred to the charge storage region 13.
Then, when the transfer transistor 8 is turned off, a voltage is applied to the read control line 30 by the vertical scan circuit 26, and the transfer transistor 21 is turned on. Thus the signal charge stored in the charge storage region 13 is transferred to the FD region 14.
This operation of transferring the signal charge causes voltage variation in the FD region 14. In response to the voltage variation, a current signal is outputted from the amplification transistor 23 to the vertical signal line 33. On the other hand, a voltage is applied to the reset control line 31 by the vertical scan circuit 26, and the reset transistor 22 is turned on. Thus the voltage of the FD region 14 is reset.
The current signal outputted to the vertical signal line 33 is outputted to the horizontal signal line 34 via the CDS circuit 28 and via the horizontal selection transistor 25 which is selected by the horizontal scan circuit 27 to be turned on. Then the current signal is amplified by the amplifier 37 and outputted to the outside.
The CMOS image sensor 1 can be fabricated in the following manner.
First, as shown in
After the semiconductor substrate 2 is formed, as shown in
After the N-type impurity region 42 is formed, the resist pattern 41 is removed. Then, as shown in
After the N-type impurity region 42 is formed, as shown in
After the backside of the P-type Si substrate 3 is polished, a resist pattern (not shown) is formed on the SiO2 film 43 by photolithography. Then the resist pattern is used as a mask to etch the SiO2 film 43 by reactive ion etching (RIE). Then the resist pattern is removed. Next, as shown in
After etching is conducted to the upper portion of the P-type Si substrate 3, as shown in
After the channel stopper region 11 is formed, as shown in
After penetration of the trenches 2a, as shown in
Then, P-type impurities constituting the channel stopper region 11 and N-type impurities constituting the N-type impurity region 9 and the charge storage region 13 are diffused by annealing. While the N-type impurity region 9 and the charge storage region 13 are formed by injecting N-type impurities from both of the frontside and backside of the semiconductor substrate 2 in
Next, the inner wall of the trench 2a is thermally oxidized to form a gate insulating film 6 as shown in
After the frontside and backside of the semiconductor substrate 2 are polished, a resist pattern (not shown) is formed on the backside of the semiconductor substrate 2 by photolithography. The resist pattern is used as a mask to inject N-type impurities into the bottom of the P-type Si substrate 3 by ion implantation, thereby forming an FD region 14 at the bottom of the P-type Si substrate 3 as shown in
After the FD region 14 is formed, the resist pattern is removed. Subsequently, as shown in
Finally, as shown in
In this embodiment, because the signal processing section 20 is formed on the backside of the semiconductor substrate 2 as shown in
In the case of forming the signal processing section 20 on the backside of the semiconductor substrate 2, it is necessary to transfer the signal charge from the N-type impurity region 9 to the signal processing section 20. In this embodiment, because a charge storage region 13 is formed below the N-type impurity region 9 and a gate electrode 7 is formed in the semiconductor substrate 2, the signal charge stored in the N-type impurity region 9 can be transferred to the signal processing section 20.
In this embodiment, because the signal processing section 20 is formed on the backside of the semiconductor substrate 2, the region of the photodiode 10 in the plane of the CMOS image sensor 1 can be increased. Thus the incidence efficiency of light incident on the photodiode 10 can be further improved. In addition, because the region of the photodiode 10 can be increased (ineffective region can be reduced), the microlens 16 can be omitted on the color filter 15.
In this embodiment, in the case as shown in
In contrast, when a channel stopper region 11 is juxtaposed with the gate insulating film 6 in the longitudinal direction of the trench 2a for device isolation between the pixels P, the proportion of the trenches 2a occupying in the semiconductor substrate 2 is decreased. Thus the mechanical strength of the semiconductor substrate 2 can be prevented from decreasing.
The invention is not limited to the embodiment described above. The embodiment can be modified as appropriate in its structure and material and in the placement of its various members without departing from the spirit of the invention. For example, while a CMOS image sensor 1 is described in the above embodiment as an example of the solid-state imaging device, it may be a CCD image sensor.
In the embodiment described above, the first impurity region is the N-type impurity region 9. However, the first impurity region may be different from the N-type impurity region 9. That is, the first impurity region may be an N-type impurity region to which the signal charge is transferred directly or indirectly from the N-type impurity region 9.
In the embodiment described above, the second impurity region is the charge storage region 13. However, if the gate electrode 7 is used to transfer the signal charge from the N-type impurity region 9 to the FD region 14 without the intermediary of the charge storage region 13, the second impurity region can be the FD region 14.
FIGS. 9 to 11 are schematic configuration views of a CMOS image sensor 101 according to a second embodiment of the invention.
This embodiment differs from the first embodiment described above in that an overflow drain unit 31 is provided generally at the center of the channel stopper region 11 serving for device isolation between adjacent pixels P, and in that a P-type impurity layer 32 is provided opposite to the channel stopper region 11 and the overflow drain unit 31. The rest of the configuration is the same as the previous embodiment. The same elements as those in the previous embodiment are marked with the same reference numerals.
As shown in
Because of the multilayer structure as described above, the thickness of the semiconductor substrate 2 can be varied as appropriate on the order of several micrometers to several hundreds of micrometers depending on the thickness of the constituent layers.
The P-type Si substrate 3 and the P-type epitaxial layer 5 illustratively have an impurity concentration of about 1.0×1018/cm3, and the P+-type epitaxial layer 4 illustratively has an impurity concentration of about 1.0×1020/cm3. The total thickness of the P+-type epitaxial layer 4 and the P-type epitaxial layer 5 is illustratively about 5 to 10 μm.
The semiconductor substrate 2 has trenches 2a that penetrate the semiconductor substrate 2 in the thickness direction. The trench 2a illustratively has a width of about 0.8 μm.
A gate insulating film 6 is formed on the inner wall of the trench 2a, and a gate electrode (a first gate electrode) 7 is formed inside the gate insulating film 6. As with the previous embodiment, in response to application of voltage, the gate electrode 7 serves to read a signal charge, which has been stored in an N-type impurity region 9, and to transfer the signal charge to a charge storage region 13. That is, this portion constitutes a transfer transistor 8, where the source is the N-type impurity region 9, the gate is the gate electrode 7, and the drain is the charge storage region 13. Through the read control line 29 described in the previous embodiment, a common voltage is applied to the gate electrodes 7 adjacent to each other in the width direction of the trench 2a (horizontally across page in
An N-type impurity region 9 is formed as a first impurity region on the P-type epitaxial layer 5, which is the surface layer of the semiconductor substrate 2. One of the side faces of the N-type impurity region 9 is adjacent to the gate electrode 7 via the P-type impurity region 32 and the gate insulating film 6. The P-type epitaxial layer 5 and the N-type impurity region 9 constitute a photodiode 10, which is a photoelectric conversion section for converting incident light into a signal charge. The signal charge produced by photoelectric conversion is stored in the N-type impurity region 9.
The bottom of the P-type impurity region 32 is deeper than the bottom of the N-type impurity region 9 and adjacent to the upper face of the P+-type epitaxial layer 4. As shown in
The channel stopper region 11 is a P+-type impurity region and formed in the upper portion of the P-type epitaxial layer 5, the P+-type epitaxial layer 4, and the P-type Si substrate 3. The side face of the channel stopper region 11 is adjacent to the gate insulating film 6 of the neighboring pixel P. That is, the channel stopper region 11 is juxtaposed with the gate insulating film 6 in the width direction of the trench 2a (horizontally across page in
The channel stopper region 11 is juxtaposed with the gate insulating film 6 in the longitudinal direction of the trench 2a (vertically across page in
In FIGS. 9 to 11, device isolation between the pixels P in the width direction of the trench 2a is provided by the gate insulating film 6 and the channel stopper region 11. On the other hand, device isolation between the pixels P in the vertical direction (perpendicular to the page) is provided by a channel stopper region 12, which is a P+-type impurity region formed in the semiconductor substrate 2 in this portion, as shown in
Below the N-type impurity region 9 and in the P-type Si substrate 3, a charge storage region 13 is formed as a second impurity region to which the signal charge stored in the N-type impurity region 9 is transferred. The charge storage region 13 is an N-type impurity region. One of its side faces is adjacent to the gate electrode 7 via the gate insulating film 6, and the upper face of the charge storage region 13 is adjacent to the bottom of the P+-type epitaxial layer 4.
As described in the previous embodiment, at the bottom of the P-type Si substrate 3 is formed an FD region (a sixth impurity region) 14, which is a portion of a signal processing section 20 and to which the signal charge stored in the charge storage region 13 is transferred. The FD region 14 is an N-type impurity region. As described in the previous embodiment, when the signal charge stored in the charge storage region 13 is transferred to the FD region 14, a voltage is applied to a gate electrode (a second gate electrode) 21a of a transfer transistor 21.
On the other hand, as shown in
These three overflow drain layers result from the manufacturing method described below. In order that the whole of these layers functions as an overflow drain unit, the N-type impurity concentration of each overflow drain layer, particularly the first overflow drain layer 31a, needs to be lower than the N-type impurity concentration in the N-type impurity region 9.
In the first embodiment described above, when the amount of light (mainly in the visible wavelength band) incident on the photodiode 10, which is composed of the P-type epitaxial layer 5 and the N-type impurity region 9, is more than the allowable level for the photodiode 10, excess electrons are produced by photoelectric conversion. The excess electrons flow into the adjacent pixels and the like and will be detected as noise.
In contrast, in the present embodiment, an overflow drain unit 31 is provided as described above. Hence excess electrons produced by light (mainly in the visible wavelength band) incident on the N-type impurity region 9 of the photodiode 10 in an amount more than the allowable level travel through the overflow drain unit 31, the drain portion of the reset transistor 22 (not shown), and the drain line and are ejected outside the semiconductor substrate 2. This can prevent the excess electrons from flowing into the adjacent pixels and causing noise.
Furthermore, in this embodiment, the above-described P+-type impurity layer 32 is provided as shown in
The first overflow drain layer 31a in the overflow drain unit 31 preferably has an N-type impurity concentration about an order of magnitude lower than that of the N-type impurity region 9, and specifically, can be 5×1015 cm−3 to 1×1016 cm−3. The second overflow drain layer 31b preferably has an N-type impurity concentration about an order of magnitude higher than that of the N-type impurity region 9, and specifically, can be 1×1017 cm−3 to 5×1017 cm−3. The N-type impurity region 9 preferably has an N-type impurity concentration of 5×1016 cm−3 to 1×1017 cm−3.
On the frontside of the semiconductor substrate 2, a color filter 15 is formed. On the color filter 15 is formed a microlens 16, which serves as a lens for focusing light and guiding the light to the photodiode 10.
On the backside of the semiconductor substrate 2 (backside of the P-type Si substrate 3) is formed a signal processing section 20 to which the signal charge transferred to the charge storage region 13 is inputted. As shown in
The transfer transistor 21 and the following elements are not described here because they are the same as those in the first embodiment described above.
The CMOS image sensor 101 of this embodiment can also be operated similarly to the first embodiment described above using the circuit as shown in
In this embodiment again, because the signal processing section 20 is formed on the backside of the semiconductor substrate 2, light incident on the photodiode 10 formed in the semiconductor substrate 2 suffers no interference from interconnects and the like of the signal processing section 20. Thus, even the light obliquely incident on the photodiode 10 can reach the photodiode 10. As a result, the incidence efficiency of light incident on the photodiode 10 can be improved.
Furthermore, because a charge storage region 13 is formed below the N-type impurity region 9 via the P+-type impurity layer 32 and a gate electrode 7 is formed in the semiconductor substrate 2, the signal charge stored in the N-type impurity region 9 can be transferred to the signal processing section 20 by this transfer transistor 8.
Moreover, because the photodiode 10 is formed on the frontside of the semiconductor substrate 2 whereas the signal processing section 20 is formed on the backside of the semiconductor substrate 2, the region of the photodiode 10 in the plane of the CMOS image sensor 101 can be increased. Thus the incidence efficiency of light incident on the photodiode 10 can be further improved. In addition, because the region of the photodiode 10 can be increased (ineffective region can be reduced), the microlens 16 can be omitted on the color filter 15.
Furthermore, as shown in
The CMOS image sensor 101 in this embodiment can be fabricated in the following manner.
First, as shown in
Next, as shown in
Next, as shown in
Next, the resist pattern 44 is removed. Then, as shown in
Next, as shown in
After the backside of the P-type Si substrate 3 is polished, a resist pattern (not shown) is formed on the SiO2 film 43 by photolithography. Then the resist pattern is used as a mask to etch the SiO2 film 43 by reactive ion etching (RIE). Then the resist pattern is removed. Next, as shown in
Next, as shown in
Next, the inner wall of the trench 2a is thermally oxidized to form a gate insulating film 6 as shown in
Next, a resist pattern (not shown) is formed on the backside of the semiconductor substrate 2 by photolithography. The resist pattern is used as a mask to inject N-type impurities into the bottom of the P-type Si substrate 3 by ion implantation, thereby forming an FD region 14 at the bottom of the P-type Si substrate 3 as shown in
In view of efficiency, it is preferable that the gate electrode 21a be formed from the same material (e.g., aluminum) and in the same process as the interconnect pad formed in the signal processing section 20. However, the gate electrode 21a may be formed by using poly-Si in a separate process from that for the interconnect pad.
Next, as shown in
The invention has been described in detail with reference to the examples. However, the invention is not limited to the foregoing description, but can be varied or modified without departing from the scope of the invention.
Number | Date | Country | Kind |
---|---|---|---|
2005-257085 | Sep 2005 | JP | national |
2006-195075 | Jul 2006 | JP | national |