Patent Application
20070018271
1. Filed of the Invention
This invention is related to bonding pads of an integrated circuit, particularly to the control pad of a digital integrated circuit.
2. Brief Description of Related Art
FIG. 1 shows the layout of bonding pads of a prior art digital integrated circuit (IC)10. There are a plurality of input/output (I/O) pads 17 for an IC. Here in FIG. 1, only two I/O pads are shown as an example. A control pad 11 is shown to offer multi-functional definition. The signal for the conventional control pad is either logical “1” customarily coupled to the positive supply voltage Vdd for positive logic as shown in FIG. 1(a), or logical “0” coupled to the negative supply voltage Vss as shown in FIG. 1(b). The status of the conventional control pad is tabulated in Table 1A. The conventional control pad is either connected to Vdd or connected to Vss.
An object of the present invention is to furnish more than two control signals from a split control pad that occupies only a single pad area. Another object of the invention is to use one or more control pad as a decoder.
These objects are achieved by splitting a control pad into two sections. One section is connected to Vdd through a first high resistance, and supplies internal signal 1. A second section is connected to Vss through a second high resistance, and supplies internal signal 2.
When the control pad is not bonded, the first section is pulled up to Vdd and the second section is pulled down to Vss, and internal signal 1 and signal 2 represent as (1,0).
When a logical “1” is bonded to both sections with a single bonding bump, the internal signal 1 and signal 2 represent logic (1,1). When a logical “0” is bonded to both sections with a single bonding bump, the internal signal 1 and signal 2 represent logic (0,0).
More than one split control pad can be designed in for a longer than two bit digital word to be decoded.
FIG. 1(a) shows a prior art with one control pad bonding to Vdd; FIG. 1(b) shows the prior art with the control pad bonding to Vss
FIG. 2 shows the split control pad of the present invention to preset to (1,0) by high resistance circuit.
FIG. 3 shows the split control pad of the present invention to preset to (1,1) by bonding to Vdd.
FIG. 4 shows the split control pad of the present invention to preset to (0,0) by bonding to Vss.
FIG. 2 shows the first embodiment of the present invention. A control pad 21 that occupies substantially the same area of the other pad, is located on an IC chip 20. The control pad 21 is split into a left section L and a right section R. The L section is internally connected to a positive supply voltage Vdd through a resistor RL, say the left hand one. The R section is internally connected to a negative supply voltage Vss through a second resistor RR, say the right hand one. In this configuration, two sections of the split control pad 21 are impressed with logical word “1,0”. This status is denoted as S2, Default in Table 1B.
FIG. 3 shows a second embodiment of the present invention. In this configuration, the split control pad 21 is bonded through wire 22 to a voltage source Vdd, the bonding bump 23 covers both sections. Then both L and R sections of the split control pad 21 are forced to maintain a same voltage Vdd. Thus the two sections of the split control pad 21 are impressed with logical word “1,1”. This status is denoted as S1, Selection 1 in Table 1B.
FIG. 4 shows a third embodiment of the present invention. In this configuration, the split control pad 21 is bonded through wire 22 to a voltage source Vss, the bonding bump 23 covers both sections. Then, both sections of the split control pad 21 are forced to maintain a same voltage Vss. Thus, the two sections of the split control pad 21 are impressed with a logical word “0,0”. This status is denoted as S0, Selection 2 in Table 1B.
More logic word combinations can be obtained by using more than one split control pads. Table 2 shows possible logic word combinations of two 2-section split control pads, Split Pad 1 and Split Pad 2, combination. For each status of Split Pad 1, there can be three status of Split Pad 2, as shown in Table 2 with a total of 9 different status. In this Table 2, L, R represent the left section and right section respectively. The control pad first decodes “0,0” as S0; “1,1” as S1; “1,0” as S2 as defined in Table 1B. Then “S0, S0” is decoded as T0; “S0,S1” as T1; “S0,S2” as T2; “S1,S0” as T3; “S1,S1” as T4; “S1,S2” as T5; “S2,S0” as T6; “S2,S1” as T7; and “S2,S2” as T8.
In FIGS. 2, 3 and 4, the control pad is split into two sections. The embodiments can be extended to split the control pad into more than two sections, each section connected to a different voltage source through a resistor.
While the embodiments of the invention have been described, it will be apparent to those skilled in the art that various modifications can be made without departing from the spirit of the invention. Such modifications are all within the scope of this invention.
