Patent Application
20250008719
The present disclosure generally relates to semiconductor device fabrication, and more particularly, to an SRAM formation for vertical FET with backside contact.
In semiconductor device manufacture, static random-access memory (SRAM) devices are incorporating next generation technologies including, for example, vertical field effect transistors (VFET). The formation of VFET devices poses many challenges in the effort to connect different device elements. For example, some current VFET structures that incorporate a pull-up and pull-down inverter connect the source and drain areas through a doped semiconductor area. Using the doped semiconductor can induce higher resistance and low speed signaling. In another proposed approach, the source and drain are connected through a metal line under the metal gate. To provide connectivity, the metal line wraps around the source and drain areas of the pull-up/pull-down elements, the gate, and a cross-couple contact. The metal line under the source and drain areas uses additional wiring to connect to the top side of the device.
According to another embodiment of the present disclosure, a semiconductor chip device is provided. The semiconductor device includes a source and drain bottom epitaxial layer. A metal gate is positioned on top of the bottom epitaxial layer. A source and drain top epitaxial layer is positioned on top of the metal gate. A first semiconductor channel is positioned passing vertically from the source and drain top epitaxial layer through the metal gate to the source and drain bottom epitaxial layer. A second semiconductor channel is positioned passing vertically from the top epitaxial layer through the metal gate to the source and drain bottom epitaxial layer. A first metal contact is conductively coupled to the first semiconductor channel. A second metal contact is conductively coupled to the second semiconductor channel. A first metal via is on a backside of the source and drain bottom epitaxial layer and arranged in conductive contact with the first semiconductor channel. A second metal via is on the backside of the source and drain bottom epitaxial layer and arranged in conductive contact with the second semiconductor channel. A metal layer is on a backside of the first and second metal vias.
According to an embodiment of the present disclosure, a vertical FET device is provided. The device includes a first frontside metal gate. A first pull-up transistor element is arranged vertically in the first frontside metal gate. A first pull-down transistor element is arranged vertically in the first frontside metal gate. A first metal layer is positioned under a backside of the first frontside metal gate and electrically couples the first pull-up transistor element to the first pull-down transistor element. A second frontside metal gate is included in the device. A second pull-up transistor element is arranged vertically in the second frontside metal gate. A second pull-down transistor element is arranged vertically in the second frontside metal gate. A second metal layer electrically couples the second pull-up transistor element to the second pull-down transistor element. A first cross-couple conductive metal is in contact with the first frontside metal gate and the second metal layer.
According to an embodiment of the present disclosure, a method of fabricating a semiconductor device is provided. The method includes providing an initial semiconductor structure. An initial semiconductor structure including a dielectric substrate is provided. A source and drain bottom epitaxial layer positioned on top of the dielectric substrate is provided. A metal gate positioned on top of the bottom epitaxial layer and the dielectric substrate is provided. A source and drain top epitaxial layer positioned on top of the metal gate is provided. A first semiconductor channel passing vertically from the source and drain top epitaxial layer through the metal gate to the source and drain bottom epitaxial layer is provided. A second semiconductor channel passing vertically from the top epitaxial layer through the metal gate to the source and drain bottom epitaxial layer is provided. A first metal contact is conductively coupled to the first semiconductor channel. A second metal contact is conductively coupled to the second semiconductor channel. A first metal via is formed on a backside of the source and drain bottom epitaxial layer and arranged in conductive contact with the first semiconductor channel. A second metal via is formed on the backside of the source and drain bottom epitaxial layer and arranged in conductive contact with the second semiconductor channel. A metal layer is formed on a backside of the first and second metal vias.
The techniques described herein may be implemented in a number of ways. Example implementations are provided below with reference to the following figures.
The drawings are of illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be practiced with additional components or steps and/or without all of the components or steps that are illustrated. When the same numeral appears in different drawings, it refers to the same or like components or steps.
Vertical field effect transistor (VFET) fabrication generally involves complex pattern formations in the vertical planes. Conventional VFET fabrication techniques commonly connect elements together using wiring from a wafer's frontside. Since many of the VFET elements are arranged vertically on the wafer, connecting the VFET elements to shared conductive features can be challenging from a lithography perspective. In applications that use pass-gate and cross-coupled inverter pairs for example, wrap-around metallization may be used to ensure connectivity between the many various elements. However, wrap-around formations require substantial patterning around other features. Thus, more complexity is added to the fabrication processes used to manufacture a VFET. In addition, the spacing between the wrap around metal and the metal gate can be narrow enough that a high-K parasitic capacitance may be introduced.
In general, the subject disclosure describes a process for providing a semiconductor device that includes forming a VFET structure. The VFET of the subject disclosure may include a pull-up/pull-down inverter. The VFET may be used in for example, a static random-access memory (SRAM) device. The semiconductor device provides an improvement over conventional VFET devices by including a metal layer and conductive contacts formed on the backside of the VFET. The metal layer provides a shared connection for the pull-up and pull-down elements in the inverter. In addition, the metal layer connects one inverter in the SRAM device to an adjoining inverter via a cross-couple element without needing to resort to complicated feature patterning such as wrap-around metallization. It should also be appreciated that the backside contacts space the backside metal layer from the metal in the gate region of the inverter. The spacing formed between metal layers of the subject device is wider than the spacing present in some wrap-around metal connects for known VFET designs, thus lowering the parasitic capacitance in the backside of the device.
For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.
In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and/or circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings.
In one aspect, spatially related terminology such as “front,” “back,” “top,” “bottom,” “beneath,” “below,” “lower,” above,” “upper,” “side,” “left,” “right,” and the like, is used with reference to the direction of the Figures being described. Since components of embodiments of the disclosure can be positioned in a number of different directions, the directional terminology is used for purposes of illustration and is in no way limiting. Thus, it will be understood that the spatially relative terminology is intended to encompass different directions of the device in use or operation in addition to the direction depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation that is above, as well as, below. Similarly, an element described as “on top of” of another element may mean either that the element is positioned above and is not necessarily in direct contact with the underlying element. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other directions) and the spatially relative descriptors used herein should be interpreted accordingly.
As used herein, the terms “lateral”, “planar”, and “horizontal” describe an orientation parallel to a first surface of a chip or substrate. In the disclosure herein, the “first surface” may be the top layer of a semiconductor device where individual circuit devices are patterned in the semiconductor material.
As used herein, the term “vertical” describes an orientation that is arranged perpendicular to the first surface of a chip, chip carrier, chip substrate, or semiconductor body.
As used herein, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together-intervening elements may be provided between the “coupled” or “electrically coupled” elements. In contrast, if an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. The term “electrically connected” refers to a low-ohmic electric connection between the elements electrically connected together. The phrase “electrically connected” does not necessarily mean that the elements must be directly in physical contact together-intervening elements may be provided between the “connected” or “electrically connected” elements.
Although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. Nor does describing an element as “first” or “second”, etc. necessarily mean that there is an order or priority to any of the elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope. It should be appreciated that the figures and/or drawings accompanying this disclosure are exemplary, non-limiting, and not necessarily drawn to scale.
It is to be understood that other embodiments may be used, and structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.
In the following, a process describes a general method of forming a semiconductor device that uses a backside conductive connection for an inverter pair. In some embodiments, the backside connection provides a conductive element for cross-coupling to an adjoined inverter pair of for example, a SRAM device. The fabrication of the devices described herein below can comprise multi-step sequences of, for example, photolithographic and/or chemical processing steps that facilitate gradual creation of electronic-based systems, devices, components, and/or circuits in a semiconducting and/or a superconducting device (e.g., an integrated circuit). For instance, devices discussed herein can be fabricated on one or more substrates (e.g., a silicon (Si) substrates, and/or another substrate) by employing techniques including, but not limited to: photolithography, microlithography, nanolithography, nanoimprint lithography, photomasking techniques, patterning techniques, photoresist techniques (e.g., positive-tone photoresist, negative-tone photoresist, hybrid-tone photoresist, and/or another photoresist technique), etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, and/or another etching technique), evaporation techniques, sputtering techniques, plasma ashing techniques, thermal treatments (e.g., rapid thermal anneal, furnace anneals, thermal oxidation, and/or another thermal treatment), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical-mechanical planarization (CMP), backgrinding techniques, and/or another technique for fabricating an integrated circuit.
In
Vertically formed FET channels 125 may be formed over the substrate 105. One FET channel 125 may be configured as a PFET (or P-channel) and the other channel 125 may be configured as an NFET (or N-channel). The channels 125 may share a metal gate 130. The backside of the channels 125 may be coupled to a backside epitaxial layer 110B. The frontside of the channels 125 may be coupled to a frontside epitaxial layer 110F. The metal gate 130 region may be isolated from frontside elements by a frontside spacer 120T and isolated from backside elements by a backside spacer 120B. Some embodiments may include a gate dielectric 123 and a work function metal 127 isolating the channels 125 from the metal gate 130. Some embodiments may include an interlevel dielectric 115 to insulate the regions around the backside epitaxial layer 110B. Some embodiments may include interlevel dielectric 115 to insulate the regions surrounding the frontside epitaxial layer 110F. Metal vias 140 may be connected to each frontside epitaxial layer 110F. Frontside metal contacts 145 may be electrically connected to each via. An insulator 135 may be present and configured to insulate the vias 140 and metal contacts 145 of each channel from each other. Some embodiments may include a back end of line (BEOL) layer 150 positioned on the frontside of the device and over the metal contacts 145.
The descriptions of the various embodiments of the present teachings have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
While the foregoing has described what are considered to be the best state and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.
The components, steps, features, objects, benefits and advantages that have been discussed herein are merely illustrative. None of them, nor the discussions relating to them, are intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, magnitudes, sizes, and other specifications that are set forth in this specification, including in the claims that follow, are approximate, not exact. They are intended to have a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they pertain.
Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional, and/or different components, steps, features, objects, benefits, and advantages. These also include embodiments in which the components and/or steps are arranged and/or ordered differently.
While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term “exemplary” is merely meant as an example, rather than the best or optimal. Except as stated immediately above, nothing that has been stated or illustrated is intended or should be interpreted to cause a dedication of any component, step, feature, object, benefit, advantage, or equivalent to the public, regardless of whether it is or is not recited in the claims.
It will be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein. Relational terms such as first and second and the like may be used solely to distinguish one entity or action from another without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “a” or “an” does not, without further constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.
The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.
