Stacked semiconductor device

Abstract

A stacked semiconductor device includes a first semiconductor element bonded on a circuit base. The first semiconductor element is electrically connected to a connection part of the circuit base via a first bonding wire. A second semiconductor element is bonded on the first semiconductor element via a second adhesive layer with a thickness of 50 μm or more. The second adhesive layer is formed of an insulating resin layer whose glass transition temperature is 135° C. or higher and whose coefficient of linear expansion at a temperature equal to or lower than the glass transition temperature is 100 ppm or less.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing the structure of a stacked semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a modified example of the stacked semiconductor device shown in FIG. 1.

FIG. 3 is a graph showing an example of an influence that a coefficient of linear expansion of a second adhesive layer in the stacked semiconductor device has on a value of a surface tensile stress of a semiconductor element at the time of a thermal cycle test.

FIG. 4 is a graph showing an example of an influence that a thickness of the second adhesive layer and a thickness of the semiconductor element in the stacked semiconductor device have on a value of a surface tensile stress of the semiconductor element at the time of a thermal cycle test; and

FIG. 5 is a chart showing a percent defective (cumulative percent defective) in a thermal cycle test of a stacked semiconductor device according to a comparative example.

Claims

1. A stacked semiconductor device, comprising: a circuit base having an element mounting part;a first semiconductor element bonded on the element mounting part of the circuit base; anda second semiconductor element bonded on the first semiconductor element via an adhesive layer with a thickness of 50 μm or more,wherein the adhesive layer is formed of an insulating resin layer whose glass transition temperature is 135° C. or higher and whose coefficient of linear expansion at a temperature equal to or lower than the glass transition temperature is 100 ppm or less.

2. The stacked semiconductor device as set forth in claim 1, wherein the adhesive layer has the thickness within a range from 70 μm to 150 μm.

3. The stacked semiconductor device as set forth in claim 1, wherein each of the first and second semiconductor elements has a thickness of 70 μm or less.

4. The stacked semiconductor device as set forth in claim 3, wherein the insulating resin layer has the coefficient of linear expansion of 70 ppm or lower.

5. The stacked semiconductor device as set forth in claim 1, wherein the circuit base has a connection part, and the first semiconductor element has an electrode part electrically connected to the connection part of the circuit base via a first bonding wire.

6. The stacked semiconductor device as set forth in claim 5, wherein the second semiconductor element has an electrode part electrically connected to the connection part of the circuit base via a second bonding wire.

7. A stacked semiconductor device, comprising: a circuit base having an element mounting part and a connection part;a first semiconductor element bonded on the element mounting part of the circuit base and having an electrode part;a second semiconductor element bonded on the first semiconductor element via an adhesive layer with a thickness of 50 μm or more and having an electrode part;a first bonding wire which electrically connects the connection part of the circuit base and the electrode part of the first semiconductor element to each other and whose end portion connected to the first semiconductor element is buried in the adhesive layer; anda second bonding wire electrically connecting the connection part of the circuit base and the electrode part of the second semiconductor element to each other,wherein the adhesive layer is formed of an insulating resin layer whose glass transition temperature is 135° C. or higher and whose coefficient of linear expansion at a temperature equal to or lower than the glass transition temperature is 100 ppm or less.

8. The stacked semiconductor device as set forth in claim 7, wherein the adhesive layer has the thickness within a range from 70 to 150 μm.

9. The stacked semiconductor device as set forth in claim 7, wherein each of the first and second semiconductor elements has a thickness of 70 μm or less.

10. The stacked semiconductor device as set forth in claim 9, wherein the insulating resin layer has the coefficient of linear expansion of 70 ppm or less.

11. The stacked semiconductor device as set forth in claim 7, wherein the first bonding wire is apart from a lower surface of the second semiconductor element due to the thickness of the adhesive layer.

12. The stacked semiconductor device as set forth in claim 11, wherein the adhesive layer has a die bonding viscosity of not lower than 1 kPa·s and lower than 100 kPa·s.

13. The stacked semiconductor device as set forth in claim 7, wherein the adhesive layer includes: a first rein layer disposed on the first semiconductor element side and softening or melting at a temperature for bonding the second semiconductor element; anda second resin layer disposed on the second semiconductor element side and maintaining a layered form at the temperature for bonding the second semiconductor element,wherein the end portion of the first bonding wire is buried in the first resin layer.

14. The stacked semiconductor device as set forth in claim 13, wherein the first resin layer has a die bonding viscosity of not lower than 1 kPa·s and lower than 100 kPa·s, andwherein the second resin layer has a die bonding viscosity of 100 kPa·s or higher.

15. The stacked semiconductor device as set forth in claim 7, wherein the second semiconductor element has a substantially same shape as the first semiconductor element or a shape larger than the first semiconductor element.

16. The stacked semiconductor device as set forth in claim 7, wherein the circuit base has an external connection terminal which is formed on a surface opposite a surface where the element mounting part is provided.