Patent Application
20240203984
The present invention generally relates to semiconductor device fabrication and, more particularly, to the fabrication of stacked nanosheet transistors.
Stacked transistor devices may be used to increase the areal density of devices on a chip. Additionally, the close proximity of the overlying and underlying devices can be useful when forming paired devices, such as complementary semiconductor devices that include two devices of opposing polarity. However, positioning transistors above one another can make it challenging to form signal- and power-bearing connections to the gate and source/drain structures of the underlying device.
A semiconductor device includes a lower semiconductor device over a substrate, the lower semiconductor device having a first width. An upper semiconductor device is over the lower semiconductor device. The upper semiconductor device has a second width smaller than the first width. A dielectric structure is over the lower semiconductor device and has a first sidewall that faces the upper semiconductor device and a second sidewall that aligns vertically with a sidewall of the lower semiconductor device.
A semiconductor device includes a lower semiconductor device over a substrate, the lower semiconductor device having a first width. An upper semiconductor device is over the lower semiconductor device. The upper semiconductor device has a second width smaller than the first width. A dielectric liner is on a side of a channel layer of the upper semiconductor device and is formed from a first dielectric material. A dielectric structure is over the lower semiconductor device. The dielectric structure has a first sidewall that faces the upper semiconductor device and the dielectric liner and a second sidewall that aligns vertically with a sidewall of the lower semiconductor device and is formed from a second dielectric material different from the first dielectric material.
A method of forming a semiconductor device includes etching an upper stack of layers from a series of alternating semiconductor layers using a top dielectric layer as a mask. A dielectric spacer is formed on a sidewall of the upper stack of layers. A lower stack of layers is etched from the series of alternating semiconductor layers, using the top dielectric layer and the dielectric spacer as a mask. A lower transistor is formed from the lower stack of layers. An upper transistor is formed from the upper stack of layers.
These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The following description will provide details of preferred embodiments with reference to the following figures wherein:
A stepped structure may be used when forming stacked transistors, for example by trimming the upper transistor area to expose a portion of the lower transistor area. The stepped profile makes it possible to form conductive contacts with vias that reach straight down to the underlying device. Rather than using a lithography-etch-lithography-etch process to define the locations of the upper and lower devices, a placeholder dielectric may be formed on a sidewall of the upper transistor and may be used as a mask to define the area of the lower transistor. Using the placeholder dielectric as a mask prevents mask placement errors that may arise when the lithography placement resolution comes close to the difference in size between the top transistor and the bottom transistor.
Referring now to
A first cross-section, AA, establishes a plane that cuts vertically through the top channel layer 104 and the bottom channel layer, and further cuts through the dielectric placeholder 106. A second cross-section, BB, establishes a plane that cuts vertically through the top channel layer 104 and the bottom channel layer, parallel to the dielectric placeholder 106 but not through the dielectric placeholder 106. A third cross-section, CC, establishes a plane that cuts vertically through the bottom channel layer and the dielectric placeholder 106, but does not cut through the top channel layer 104.
As shown, the cross-section AA cuts through what may become a gate/channel section of the top transistor device and the bottom transistor device. For the steps described herein, the structures and processes shown in the gate/channel section may be identical to those of the source/drain section. However, it may be understood that these different regions may undergo different processes to produce the different functional structures of a transistor device.
Referring now to
A buffer layer 206 may be formed from the same semiconductor material as the sacrificial semiconductor layers 202 to separate channels of the top device from channels of the bottom device. In some cases, the buffer layer 206 may include a dielectric layer that electrically separates the top set of layers from the bottom set of layers, or a layer of silicon germanium. The buffer layer 206 may have a thickness that is between about 1.5-2 times greater than a thickness of the sacrificial semiconductor layers 202.
A mask layer 208 may be formed over the stack of alternating semiconductor layers. The mask layer 208 may be formed from any appropriate masking material, and may include multiple layers of such material. For example, the mask layer 208 may include a layer of a first dielectric material (e.g., silicon nitride) sandwiched between layers of a second dielectric material (e.g., silicon dioxide). A layer of amorphous silicon 210 may be formed over the mask layer 208. A lithographic pattern 212 may then be formed over the amorphous silicon 210, and may be used to establish a location of a top transistor device.
The semiconductor substrate 102 may be a bulk-semiconductor substrate. In one example, the bulk-semiconductor substrate may be a silicon-containing material. Illustrative examples of silicon-containing materials suitable for the bulk-semiconductor substrate include, but are not limited to, silicon, silicon germanium, silicon germanium carbide, silicon carbide, polysilicon, epitaxial silicon, amorphous silicon, and multi-layers thereof. Although silicon is the predominantly used semiconductor material in wafer fabrication, alternative semiconductor materials can be employed, such as, but not limited to, germanium, gallium arsenide, gallium nitride, cadmium telluride, and zinc selenide. Although not depicted in the present figures, the semiconductor substrate 102 may also be a semiconductor on insulator (SOI) substrate.
As noted above, the stack of alternating semiconductor layers may be epitaxially grown from the top surface of the semiconductor substrate 102. The terms “epitaxial growth” and “epitaxial deposition” are used herein to refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has substantially the same crystalline characteristics as the semiconductor material of the deposition surface. The term “epitaxial material” denotes a material that is formed using epitaxial growth. Thus, for example, if the semiconductor substrate 102 is formed from silicon, then the sacrificial semiconductor layers 202 may include a silicon germanium material and the channel layers 204 may include silicon, as these materials have similar crystalline structure. In some embodiments, when the chemical reactants are controlled and the system parameters set correctly, the depositing atoms arrive at the deposition surface with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Thus, in some examples, an epitaxial film deposited on a {100} crystal surface will take on a {100} orientation.
The pattern 212 may be formed using any appropriate photolithographic process. For example, the pattern 212 may be produced by applying a photoresist to the surface to be etched. The photoresist may be exposed to a pattern of radiation, which may for example cure the exposed part of the photoresist. The pattern may be developed into the photoresist utilizing a resist developer that removes the portion of the photoresist material that was not cured. The result is a pattern 212 of material that covers and protects an area of the underlying surface(s).
Referring now to
As used herein, the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied. Thus, the selective anisotropic etches described with respect to the formation of the upper stack 304 may remove the semiconductor material of the alternating semiconductor layers, without substantially damaging the material of the mask 302.
The anisotropic etches may include, for example, reactive ion etching (RIE). RIE is a form of plasma etching in which during etching the surface to be etched is placed on a radio-frequency powered electrode. Moreover, during RIE the surface to be etched takes on a potential that accelerates the etching species extracted from plasma toward the surface, in which the chemical etching reaction is taking place in the direction normal to the surface.
Referring now to
A layer 404 of dielectric material is conformally deposited over the upper protective layer 402. The layer 404 of dielectric material may include any dielectric material with appropriate etch selectivity relative to the other materials of the device, such as silicon nitride (SiN), silicoboron carbonitride (SiCBN), silicon oxycarbonitride (SiOCN), or any other appropriate dielectric material that has etch selectivity with respect to silicon dioxide. It is specifically contemplated that the dielectric layer 404 may be formed from a low-k dielectric material. A low-k dielectric is one that has a dielectric constant lower than that of silicon dioxide. A low-k dielectric may be used to, e.g., minimize a parasitic capacitance resulting from the presence of a dielectric spacer within the gate conductor of a device.
The dielectric layer 404 may be deposited to a thickness that corresponds to a difference in the ultimate size between the upper device and the lower device, as the layer 404 will form part of a mask that is used to define the size of the lower device. As seen in cross-section CC, the dielectric material of the layer 404 may occupy the space at the side of the upper stack 304.
Referring now to
Referring now to
Referring now to
Referring now to
Referring now to
Referring now to
The upper stack 304, the dielectric spacer 902, and the remaining portions of the upper protective layer 402 are used as a mask for one or more selective anisotropic etches that remove material from the buffer layer 206 and the semiconductor layers beneath it. The etch(es) remove semiconductor material from the alternating semiconductor layers to form lower stack 1002, and may further cut into the top surface of the semiconductor substrate 102, for example establishing shallow trench isolation (STI) regions around the lower stack 1002.
Although the stepped profile is shown with a single dielectric spacer 902 on a single side of the upper stack 304, it should be understood that a similar dielectric spacer may be formed on the other side of the upper stack 304, so that there are steps on both sides of the device.
The remaining portions of the dielectric spacer 702 are shown as dielectric remnant 1006. The dielectric remnant 1006 has a sidewall that vertically aligns with a sidewall of the lower stack 1002 and has a height that extends above the upper stack 304. Between the dielectric remnant 1006 and the upper stack 304 is a remaining portion of the upper protective layer 402, shown as dielectric liner 1004. The dielectric liner 1004 has an ‘L’-shaped profile, following the stepped contour of the upper stack 304 on the lower stack 1002. One sidewall of the dielectric liner 1004 is on the sidewall of the upper stack 304, while the other sidewall of the dielectric liner 1004 aligns vertically with the sidewall of the lower stack 1002 and the dielectric remnant 1006. The dielectric liner 1004 and the dielectric remnant 1006 may have top surfaces at different heights relative to the substrate 102. The dielectric liner 1004 may have a bottom surface that aligns horizontally with a bottom surface of a lowermost channel layer in the upper stack 304.
Referring now to
After formation of the respective source/drain structures 1108, the sacrificial layers may be selectively etched away using an isotropic etch that leaves the semiconductor material of the channel layers 204 relatively undamaged. This etch may further remove remaining portions of the buffer layer 206 between the upper device 1104 and the lower device 1102.
A gate stack 1106 be formed to make contact with the channel layers of each device, for example including a gate dielectric layer (not shown), an optional work function metal (not shown), and a gate conductor. The gate stack 1106 may join the gate regions of the top device 1104 and the bottom device 1102 as shown, or may be separated into two separate gates for the respective devices. An interlayer dielectric 1110 may be deposited around the upper device 1104 and the lower device 1102, and contacts may be formed therethrough to make appropriate electrical contact with the structures of the top device 1104 and the bottom device 1102.
Referring now to
Block 1204 forms a mask 302 on the alternating semiconductor layers. The mask 302 may be formed by, e.g., depositing one or more layers of dielectric material over the alternating semiconductor layers. The one or more layers of dielectric material may include, for example, a layer of silicon nitride between layers of silicon dioxide. The mask 302 may be etched from these layers using a photolithographic mask 212 and a selective anisotropic etch that stops on the semiconductor layers.
Block 1206 etches the alternating semiconductor layers, using a selective anisotropic etch to remove material from the alternating semiconductor layers in areas that are not protected by the mask 302. The etch may be timed to stop in the buffer layer 206, thereby creating upper stack 304 of alternating semiconductor layers on the buffer layer 206.
Block 1208 forms upper protective layer 402 on the upper stack 304, for example by conformally depositing a dielectric material. Exemplary deposition processes include, e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition. CVD is a deposition process in which a deposited species is formed as a result of chemical reaction between gaseous reactants at greater than room temperature (e.g., from about 25° C. about 900° C.). The solid product of the reaction is deposited on the surface on which a film, coating, or layer of the solid product is to be formed. Variations of CVD processes include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD), Plasma Enhanced CVD (PECVD), and Metal-Organic CVD (MOCVD) and combinations thereof may also be employed. In alternative embodiments that use PVD, a sputtering apparatus may include direct-current diode systems, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In alternative embodiments that use ALD, chemical precursors react with the surface of a material one at a time to deposit a thin film on the surface. In alternative embodiments that use GCIB deposition, a high-pressure gas is allowed to expand in a vacuum, subsequently condensing into clusters. The clusters can be ionized and directed onto a surface, providing a highly anisotropic deposition.
Block 1210 forms a dielectric layer 404 over the upper protective layer 402 using a conformal deposition process. The dielectric layer 404 may be formed to any appropriate thickness, which corresponds to a difference in the size of an upper device and a lower device being formed. Block 1212 etches the dielectric layer 404 to form dielectric spacer 702. Block 1212 may form an OPL 502 and mask 504 over the dielectric layer 404, using the mask 504 to define a protected region of the dielectric layer. A selective anisotropic etch may be used to remove material from the dielectric layer 404 outside of the protected region. The mask 504 and OPL 502 may then be removed, and block 1212 may use a selective anisotropic etch to remove material from the dielectric layer 404 from horizontal surfaces, leaving the dielectric spacer 702.
Block 1214 etches down into the exposed portions of the lower alternating semiconductor layers using one or more anisotropic etches to form lower stack 1002. The anisotropic etch(es) may etch down into the surface of the semiconductor substrate 102 to form trenches. Block 1216 forms a lower transistor device on the lower stack 1002, for example by forming inner spacers on sidewalls of the sacrificial layers of the lower stack 1002, epitaxially growing source/drain structures from exposed sidewalls of the channel layers of the lower stack 1002, removing the sacrificial layers of the lower stack 1002 using an isotropic etch, and forming a lower gate stack on the exposed channel layers of the lower stack 1002. Block 1218 forms an upper transistor device on the upper stack 304, for example by masking the lower transistor device, removing the upper protective layer 402, forming inner spacers on sidewalls of the sacrificial layers of the upper stack 304, epitaxially growing source/drain structures from exposed sidewalls of the channel layers of the upper stack 304, removing the sacrificial layers of the upper stack 304 using an isotropic etch, and forming an upper gate stack on the exposed channel layers of the upper stack 304.
It is to be understood that aspects of the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps can be varied within the scope of aspects of the present invention.
It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
The present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
Methods as described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGe1-x where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.
Reference in the specification to “one embodiment” or “an embodiment”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.
It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.
Having described preferred embodiments of stacked transistors with stepped contacts (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
