Claims
- 1. A static random access memory device, comprising:
- a memory cell array including a plurality of memory cells arranged in a plurality of rows and columns,
- a plurality of bit lines, each being provided in a corresponding column in said memory cell array and connected to a memory cell in said corresponding column,
- wherein each of said memory cells comprises
- data storage means having a single input/output node for storing a data signal provided via said input/output node,
- switching means connected between a bit line of a corresponding column and said input/output node for conducting in response to row and column address signals,
- a plurality of dummy cells, each being connected to one corresponding bit line of said plurality of bit lines,
- a plurality of differential sense amplifier means, each being provided for every two adjacent columns in said memory cell array and connected between two corresponding bit lines of said plurality of bit lines,
- a plurality of dummy cell enabling means, each being provided for every two adjacent columns in said memory cell array and responsive to a column address signal selecting one of said two corresponding bit lines of said plurality of bit lines for enabling a dummy cell connected to the other of said two corresponding bit lines.
- 2. A static random access memory device, comprising:
- a memory cell array including a plurality of memory cells arranged in a plurality of rows and columns,
- a plurality of shared bit lines, each being provided for every two corresponding columns in said memory cell array and connected to a memory cell in said corresponding two columns,
- wherein each of said memory cells comprises
- data storage means having a single input/output node for storing a data signal provided via said input/output node,
- switching means connected between a shared bit line in two corresponding columns and said input/output node for conducting in response to row and column address signals,
- a plurality of dummy cells, each being connected to a corresponding one of said plurality of shared bit lines,
- a plurality of differential sense amplifier means, each being provided for every four adjacent columns in said memory cell array and connected between corresponding two shared bit lines of said plurality of shared bit lines,
- a plurality of dummy cell enabling means, each being provided for every four adjacent columns in said memory cell array and responsive to a column address signal selecting one of two corresponding shared bit lines of said plurality of shared bit lines for enabling a dummy cell connected to the other of said two corresponding shared bit lines.
Priority Claims (2)
Number |
Date |
Country |
Kind |
4-111408 |
Apr 1992 |
JPX |
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4-202603 |
Jul 1992 |
JPX |
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Parent Case Info
This application is a division of application Ser. No. 08/467,632, filed Jun. 6, 1995, now U.S. Pat. No. 5,572,469 which is a division of application Ser. No. 08/025,470, filed Mar. 3, 1993.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
3539839 |
Igarashi |
Nov 1970 |
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4984201 |
Sato et al. |
Jan 1991 |
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Foreign Referenced Citations (1)
Number |
Date |
Country |
56-107394 |
Aug 1981 |
JPX |
Non-Patent Literature Citations (4)
Entry |
"16K CMOS/SOS Asynchronous Static RAM", Roger G. Stewart et al., Digest of Technical Papers, 1979, IEEE International Solid-State Circuits Conference, pp. 104-104, 286. |
"A Dynamic Three-State Memory Cell for High-Density Associative Processors", Federick P. Herrmann et al., 1990 Symposium on BLSI Circuits, p. 73-74. |
"A Novel Cell Structure for 4M Bit Full Feature EEPROM and Beyond", N. Ajika et al., Technical Digest, International Electron Devices Meeting 1991, pp. 11.1.1-11.1.4. |
"Non-Inverting Conditions of a Flipflop Circuit", Institute of Electronics, Information and Communication Engineers of Japan, Showa 54, vol. 2, pp. 2-185. |
Divisions (2)
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Number |
Date |
Country |
Parent |
467632 |
Jun 1995 |
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Parent |
25470 |
Mar 1993 |
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