Patent Application
20090302391
Integrated circuits (ICs) typically comprise numerous circuit components, such as transistors, resistors and capacitors, interconnected to perform the desired functions. Strain generation in silicon has been proposed to improve carrier mobility of transistors which decreases trapped charges in the gate oxide. Stress inducing liners are used to induce stress. However, hot electrons are more mobile than hot holes. To compensate for the differences in mobility, different stresses are applied to the p-type and n-type transistors. Dual stress inducing liners can be used to induce different stresses in respective p-type and n-type transistors. For example, a compressive stress inducing nitride liner is provided over the p-type transistors while a tensile stress inducing nitride liner is provided over the n-type transistors.
Typically, one liner overlaps the other liner to ensure that no gaps exist between the two liners. At the region where the liners overlap, the thickness is about double that of the non-overlapping regions. The non-uniformity in thickness between the overlap and non-overlap regions creates problems in subsequent processes, which can lead to decreased reliability. Furthermore, typical dual liner processes involve use of more than one mask, for example two masks, during processing. This leads to process cost and product yield concerns.
From the foregoing discussion, it is desirable to provide improved dual liners which increase reliability as well as performance of ICs.
Embodiments are generally related to semiconductor devices or integrated circuits. In one embodiment, a method of stress engineering is disclosed. The method comprises providing a substrate having first and second regions. A stress liner is deposited on the substrate. The stress liner is formed from a material having a first stress. A first portion of the stress liner over the first region is processed to convert the stress material to a second stress.
Another embodiment relates to a method of fabricating an IC. The method comprises providing a substrate having first and second active regions defined thereon. The first active region comprises a first transistor of a first type and the second active region comprises a second transistor of a second type. A stress liner is formed on the substrate covering the first and second transistors, wherein the stress liner comprises a first stress. The first portion of the stress liner over the first transistor is processed to transform the first stress of the stress liner to a second stress.
An IC that includes a first transistor of a first type on a first active region of a substrate and a second transistor of a second type on a second active region of the substrate is disclosed. A stress liner is disposed on the substrate and covers the transistors. The stress liner comprises a first portion with a first stress covering the first transistor and a second portion with a second stress covering the second transistor.
These and other objects, along with advantages and feature of the present invention herein disclosed, will become apparent through reference to the following description and the accompanying drawings. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations.
In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. Various embodiments of the present invention are described with reference to the following drawings, in which:
a-e illustrate an embodiment of a process for forming an IC;
Embodiments generally relate to semiconductor devices or ICs. The devices or ICs can be any type of device or IC, such as memory devices including dynamic random access memories (DRAMs), static random access memories (SRAMs), non-volatile memories including programmable read-only memories (PROMs) and flash memories, optoelectronic devices, logic devices, communication devices, digital signal processors (DSPs), microcontrollers, system-on-chip, as well as other types of devices. Such devices or ICs can be incorporated in various types of products, for example, computers and communication devices or systems such as phones and personal digital assistants (PDAs). Although embodiments are generally described in the context of semiconductor devices or ICs, other types of devices are also useful.
Isolating the active regions from each other and other device regions on the substrate are isolation regions 280. The isolation regions, for example, comprise STI regions. Other types of isolation regions are also useful.
The active regions comprise first and second transistors 210a-b. The first transistor comprises a first type transistor and the second transistor comprises a second type transistor. In one embodiment, the first transistor comprises a n-type transistor on the p-type doped well and the second transistor comprises a p-type transistor on a n-type doped well. A transistor includes a gate or gate stack 220. The gate stack, for example, includes a gate electrode 224 over a gate dielectric 222. Typically, the gate electrode comprises polysilicon (doped or undoped) while the gate dielectric comprises silicon oxide. Other types of gate electrode or dielectric material are also useful.
The gate stack includes dielectric spacers on the gate sidewalls. The dielectric spacers comprise, for example, a dielectric material such as oxide and/or nitride. Other types of dielectric materials are also useful. In one embodiment, each dielectric spacer comprises a L-shaped silicon oxide liner 262 on which a silicon nitride spacer 260 is disposed. Other types of spacers or spacer designs are also useful.
First and second source/drain (SD) diffusion regions 235 and 237 are provided in the substrate adjacent to the gates. In one embodiment, a diffusion region includes a shallow SD extension portion and a deep SD portion. For p-type transistors, the diffusion regions comprise p-type dopants while n-type dopants are used for n-type transistors.
Metal silicide contacts 245 can be provided on the surface of the diffusion regions and gate stack. The silicide contacts serve to reduce sheet resistance. Various types of metal silicide contacts can be used, such as nickel or nickel-alloy silicide contacts. Other type of metal silicide contacts can also be useful.
Although only one transistor is shown in each active region, it is understood that in an IC there are typically numerous transistors in an active region. For example, an active region can include densely populated (nested) or less densely populated (iso) transistors, or a combination of both. Typically, adjacent nested transistors share a common SD diffusion region. Furthermore, there may also be numerous first and second type active regions.
In accordance with one embodiment of the invention, a stress liner 270 is provided on the substrate. The stress liner comprises first and second stress portions. In one embodiment, the stress liner comprises first and second portions covering first and second transistors. The first and second portions have different stresses. For example, the first portion comprises a tensile stress while the second portion comprises a compressive stress. The tensile stress portion improves carrier mobility of the n-type transistors while the compressive stress improves carrier mobility of the p-type transistors.
The first and second portions of the stress liner, when deposited, comprise the same material. The stress liner, in one embodiment, comprises a material having a first stress. One portion of the stress liner is treated to produce a second stress while the untreated portion is maintained at the first stress. The respective stress of the different portions improves carrier mobility of the different transistors. In one embodiment, the stress liner comprises a compressive stress material. A first portion covering the n-type transistor is treated to convert it into a tensile stress material while leaving the second untreated portion with compressive stress. The stress liner, in one embodiment, comprises silicon nitride. Other types of materials are also useful. By providing a single stress layer with first and second stress portions, a smooth interface 272 between the portions results without complex processing which is required in conventional dual stress liners. As shown, the interface is located at the isolation region between the active regions.
A premetal dielectric (PMD) layer (not shown) can be provided over the substrate, separating the substrate and transistor from a metal layer. The PMD layer comprises, for example, silicon oxide. Other types of dielectric materials, such as silicon nitride, are also useful. Via plugs (not shown) are provided in the PMD layer which are coupled to metal lines of a metal layer (not shown) over the PMD layer. The plugs and metal lines form interconnections as desired.
a-e show cross-sectional views of a process for forming an IC 200 in accordance with one embodiment of the invention. Referring to
The substrate is also prepared with isolation regions 280 to separate the active regions from each other and other active device regions. In one embodiment, the isolation regions comprise STIs. Various conventional processes can be employed to form the STI regions. For example, the substrate can be etched using conventional etch and mask techniques to form trenches which are then filled with dielectric material such as silicon oxide. Chemical mechanical polishing (CMP) can be performed to remove excess oxide and provide a planar substrate top surface. The STI regions can be formed, for example, prior to or after the formation of the doped wells. Other processes or materials can also be used to form the STIs.
Transistors 210a-b are prepared in the first and second active regions. A first transistor is formed in the first active region and a second transistor is formed in the second active region. In one embodiment, the first transistor comprises a n-type transistor formed in a p-type well and the second transistor comprises a p-type transistor formed in a n-type well.
A transistor includes a gate or gate stack 220. The gate stack, for example, includes a gate electrode 224 over a gate dielectric 222. Typically, the gate electrode comprises polysilicon (doped or undoped) while the gate dielectric comprises silicon oxide. Other types of gate electrode or dielectric materials are also useful. Conventional processes can be used to form the gate stacks of the transistors. For example, gate stack layers such as gate dielectric and gate electrode are sequentially formed on the substrate. The gate stack layers are patterned to form the gate stacks. To pattern the gate stack layers, mask and etch processes can be used. The gate stack layers can be patterned to form gate conductors. A gate conductor serves as a common gate for a plurality of transistors.
The gate stack includes dielectric spacers on the gate sidewalls. The dielectric spacers comprise, for example, a dielectric material such as oxide and/or nitride. Other types of dielectric materials are also useful. In one embodiment, each dielectric spacer comprises a L-shaped silicon oxide liner 262 on which a silicon nitride spacer 260 is disposed. Other types of spacers or spacer designs are also useful. Forming the spacers can include forming a first and second dielectric layer and patterning them to form the spacers.
First and second source/drain (SD) diffusion regions 235 and 237 are provided in the substrate adjacent to the gates. The doped regions are formed by ion implantation. The implant can be self-aligned or formed using an implant mask. Other techniques for forming the diffusion regions are also useful. For p-type transistors, the diffusion regions comprise p-type dopants while n-type dopants are used for n-type transistors. The p-type and n-type diffusion regions are formed in separate implantation processes.
In one embodiment, a diffusion region includes a shallow SD extension portion and a deep SD portion. For example, shallow SD extension portions are formed after the gates are patterned and the deep SD portions are formed after spacer formation. After the formation of diffusion regions, the dopants are activated by, for example, an annealing process. The annealing also serves to facilitate recovery from any deformation to the crystal structure incurred during the process of ion implantation. Various types of annealing, such as rapid thermal annealing, spike annealing, laser spike annealing or flash lamp anneal can be used. The anneal, for example, can be performed at about 950-1300° C.
Metal silicide contacts 245 can be provided on the surface of the diffusion regions and gate stacks. The silicide contacts serve to reduce sheet resistance. Various types of metal silicide contacts can be used, such as nickel or nickel-alloy silicide contacts. Other types of metal silicide contacts are also useful. To form metal silicide contacts, a metal layer is formed over the substrate. The metal layer is processed by annealing, causing a reaction with the silicon and metal to form metal silicide contacts in the diffusion regions and gate electrode. In one embodiment, a rapid thermal anneal at a temperature of about 400-500° C. in a N2 ambient for about 5-10 sec is employed. Other process parameters may also be useful. Untreated or excess metal is removed, leaving the metal silicide contacts.
As discussed, an active region can include numerous transistors. For example, an active region can include densely populated (nested) or less densely populated (iso) transistors or a combination of both. Typically, adjacent nested transistors share a common S/D diffusion region. Furthermore, there may also be numerous first and second type active regions.
Referring to
In
In one embodiment, a stress relaxation treatment 295 is performed on the stress liner. The stress relaxation treatment comprises, in one embodiment, first and second processes. The first process comprises implanting the exposed first portion of the stress liner with stress relaxing ions. The ions, for example, comprise Ge, Xe or a combination thereof. The implant dose, for example, can be about 1e14-5e15 ions/cm2 at about 30˜70 keV. The mask protects the second portion of the stress layer over the second active region from being affected by the relaxation treatment. The relaxation treatment relaxes or reduces the stress in the first portion of the stress liner.
After ion implantation, the mask layer is removed from the second portion of the stress liner, as shown in
As shown in
It is believed that the change in stress is attributed to film shrinkage based on reflective index. Implanting the film with relaxing ions causes the film to shrink a greater amount when exposed to UV.
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the invention described herein. Scope of the invention is thus indicated by the appended claims, rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.
