Patent Application
20080157200
The present invention relates to a semiconductor structure, and more particularly to a metal oxide semiconductor field effect transistor (MOSFET) having enhanced performance.
Mechanical stresses within a semiconductor device substrate have been widely used to modulate and/or boast device performance. For example, in common Si technology, the channel of a transistor is oriented along the <110> direction on {100} planes of silicon. In this arrangement, hole mobility is enhanced when the channel is under compressive stress in the current flow direction and/or under tensile stress in a directional normal of the channel, while electron mobility is enhanced when the channel is under tensile stress in both parallel and normal direction of channel. Therefore, compressive and/or tensile stresses can be advantageously created in the channel regions of a p-channel field effect transistor (pFET) and/or an n-channel field effect transistor (nFET) in order to enhance the performance of such a device.
One possible approach for creating a desirable stressed silicon channel is to form embedded SiGe or Si:C stressors at the source and drain regions of a MOSFET to induce compressive or tensile strain in the channel region that is located between the source and drain regions. However, due to the epitaxial process nature of forming such stressors, the edge of shallow trench isolation (STI) bounded transistors contains stressor facets that diminish the benefit of the embedded stressor. Since many critical devices are STI bounded, maintaining the performance of STI bounded transistors is important for overall device enhancement.
In view of the above, there is a need for providing a semiconductor structure, particularly a MOSFET, in which the performance of STI bounded transistors is maintained.
The present invention provides an STI bounded transistor structure having enhanced performance which is not diminished due to embedded stressor facets that can be present at the edge of the source/drain regions that contacts an embedded stressor material.
Considering that the facets in the prior art are due to an STI divot formed during several necessary wet etching processes, the MOSFET source/drain edge of the inventive structure is surrounded by a liner to prevent facet growth during the epitaxial growth of the stressor material As such, a part of the semiconductor substrate edge is preserved. The liner employed in the present invention is a stress engineering material such as, for example, silicon nitride.
In another embodiment of the present invention, the upper sidewalls of the recessed semiconductor layer used in forming the embedded stressor regions as well as the upper sidewalls of the trenches used in defining the location of the STI have a nitride spacer that sticks out from the sidewalls. In this particular structure, the remaining semiconductor rim can hold the stress of the embedded stressor material. As such, there is no strain relaxation due to the presence of the ‘soft’ trench dielectric material.
In general terms, the inventive structure comprises:
a semiconductor substrate including at least one metal oxide semiconductor field effect transistor (MOSFET) located on a surface of said semiconductor substrate;
an embedded stressor material located at a footprint of each of said MOSFETs in a recessed area of semiconductor substrate; and
at least one trench isolation region located in said semiconductor substrate abutting said embedded stressor material, wherein said at least one trench isolation region is lined with a stress liner thereby preventing embedded stressor facet growth at the boundary between the at least one trench isolation region and the embedded stressor material.
In another embodiment of the present invention, the inventive structure comprises:
a semiconductor substrate including at least one metal oxide semiconductor field effect transistor (MOSFET) located on a surface of said semiconductor substrate;
an embedded stressor material located at a footprint of each of said FETs in a recessed area of said semiconductor structure;
at least one trench isolation region located in said semiconductor substrate abutting said embedded stressor material, wherein said at least one trench isolation region is lined with a stress liner thereby preventing embedded stressor facet growth at the boundary between the at least one trench isolation region and the embedded stressor material; and
a nitride spacer that sticks out from upper sidewalls of said recessed area that contains said embedded stressor material as well as upper sidewalls of trenches used in defining the at least trench isolation region.
The present invention, which provides a stress liner surrounded facetless embedded stressor MOSFET and a method of fabricating the same, will now be described in greater detail by referring to the following description and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes and, as such, they are not drawn to scale.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention However, it will be appreciated by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the invention.
It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.
As stated above, the present invention provides an STI bounded transistor structure having enhanced performance which is not diminished due to embedded stressor facets that can be present at the edge of the source/drain regions that contacts an embedded stressor material. In the present invention, the MOSFET source/drain edge is surrounded by a liner to prevent facet growth during the epitaxial growth of the stressor material. As such, a part of the semiconductor substrate edge is preserved. The liner employed in the present invention is a stress engineering material such as, for example, silicon nitride.
In particular, a semiconductor structure is provided as shown in
Reference is first made to
The initial structure 10 includes materials that are well known to those skilled in the art and it is fabricated utilizing techniques that are also well known in the art.
The semiconductor substrate 12 includes any semiconductor material including, for example, Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, InP and other III/IV or II/VI compound semiconductors. The semiconductor substrate 12 may be a bulk substrate, a layered substrate (such as Si/SiGe or a semiconductor-on-insulator (SOI)) or a hybrid substrate that has surface regions of different crystallographic orientation. A preferred semiconductor material for substrate 12 is a Si-containing semiconductor. In the drawings, the substrate 12 is a semiconductor-on-insulator wherein the buried oxide layer 12B and the upper semiconductor layer 12C are shown. A lower semiconductor layer (not shown) would be present beneath the buried oxide layer 12B.
The substrate 12 may be strained, unstrained or contain regions of strain and unstrain therein. The substrate 12 may also be undoped, doped or contain doped regions and undoped regions.
The substrate 12 may be formed utilizing conventional techniques well known to those skilled in the art. For example, a SIMOX process or a wafer bonding process can be used in forming a SOI substrate.
The pad material stack 14 is then formed atop the upper most surface of the substrate 12 utilizing a conventional deposition process and/or a thermal growing technique. A photoresist is then applied to the uppermost layer of the pad material stack 14 and then lithography is used to pattern the photoresist. Etching (drying and/or wet chemical etching) is then used to transfer the pattern from the patterned photoresist to the material stack 14 and then into the substrate 12. In the embodiment shown, the etching stops atop the upper surface of the buried oxide 12B. It is noted that the patterned photoresist can be stripped anytime after the pattern has been transferred into the pad material stack 14.
Next, and as such in
The gate dielectric 34 of each transistor may be the same or different insulating material including, for example, oxides, nitrides, oxynitrides and multilayer stacks of any of these insulators. Preferably, an oxide such as, but not limited to, silicon dioxide, is used as the gate dielectric. The gate conductor of each transistor comprises any conductive material including doped polySi, doped SiGe, an elemental metal, an alloy of an elemental metal, a metal silicide or any multilayered stack thereof (e.g., a stack of a metal silicide located atop a polySi base). Preferably, polySi gate conductors are employed. The optional dielectric cap 38 comprises an oxide, nitride or oxynitride. The gate spacer of each transistor includes an oxide, nitride, oxynitride and multilayers stacks thereof. Preferably, the spacer is an oxide or nitride of silicon.
Following the formation of the structure shown in
Following the formation of the embedded stressor material 44, conventional MOSFET processing techniques such as, for example, forming source/drain regions in the embedded semiconductor material 44, and forming silicide contacts atop the source/drain regions can be performed.
The second embodiment of the present invention begins by first providing the structure shown in
Next, as shown in
While the invention has been described herein with reference to specific embodiments, features and aspects, it will be recognized that the invention is not thus limited, but rather extends in utility to other modifications, variations, applications, and embodiments, and accordingly all such other modifications, variations, applications, and embodiments are to be regarded as being within the spirit and scope of the invention.
