BACKGROUND OF THE INVENTION
Definition
In the present application, “group III-V semiconductor” refers to a compound semiconductor that includes at least one group III element and at least one group V element, such as, but not limited to, gallium nitride (GaN), gallium arsenide (GaAs), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN) and the like. Analogously, “III-nitride semiconductor” refers to a compound semiconductor that includes nitrogen and at least one group III element, such as, but not limited to, GaN, AlGaN, InN, AlN, InGaN, InAlGaN and the like.
1. Field of the Invention
The present invention is generally in the field of semiconductor devices and their fabrication. More specifically, the present invention is in the field of group III-V power semiconductor devices and their fabrication.
2. Background Art
Group III-V semiconductor devices include group III-V materials, for example, III-nitride materials, which are typically grown over a substrate, such as, a sapphire, silicon carbide, or silicon substrate, and may provide an active area for fabrication of the semiconductor device. Silicon substrates have several advantages over other substrate materials, including their high quality, low cost, and large wafer size. However, using a silicon substrate as a support substrate for a group III-V semiconductor device can introduce various problems. For example, due to lattice mismatch and differences in thermal expansion characteristics between III-nitride materials and silicon, thick III-nitride layers can produce substantial deformation of the silicon wafer, which can in turn cause the III-nitride layers to warp and crack. As such, group III-V semiconductor devices grown using a silicon substrate typically include various layers between the active region of the device and the substrate to compensate for problems introduced when using a silicon, or other non-native, substrate. The layers can include a buffer layer formed on compositionally graded transition layers. The thickness and composition of the layers must typically be carefully controlled to prevent the undesirable warping and cracking.
However, in a group III-V semiconductor device, the thickness of its buffer layer contributes to its voltage breakdown resistance. In high power applications, it is desirable for the group III-V semiconductor device to have a high breakdown voltage, which can be achieved, in principle, using a thick buffer layer. Unfortunately, concerns about substrate deformation limit the buffer layer thickness in most conventional group III-V semiconductor devices to slightly greater than approximately 1.0 um, thereby limiting the breakdown voltage of the semiconductor device.
Thus, there is a need to overcome the drawbacks and deficiencies in the art by a solution enabling growth of thick group III-V semiconductor layers while concurrently limiting substrate deformation.
SUMMARY OF THE INVENTION
The present invention is directed to a stress modulated group III-V semiconductor device and related method, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a cross-sectional view of a group III-V semiconductor structure including a compositionally graded body having a stress modulating region, in accordance with one embodiment of the present invention.
FIG. 2 shows a flowchart presenting a method of fabricating a group III-V semiconductor device including a stress modulating compositionally graded body, in accordance with one embodiment of the present invention.
FIG. 3A shows a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an initial step in the flowchart in FIG. 2.
FIG. 3B shows a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart in FIG. 2.
FIG. 3C shows a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart in FIG. 2.
FIG. 3D shows a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to a final step in the flowchart in FIG. 2.
DETAILED DESCRIPTION OF THE INVENTION
The present invention is directed to a stress modulated group III-V semiconductor device and related method. More particularly, the present invention is directed to stress modulation in various embodiments of a novel semiconductor device including a compositionally graded body. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention. The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings.
FIG. 1 shows an exemplary semiconductor device structure including a compositionally graded body having a stress modulating region, in accordance with one embodiment of the present invention. Structure 100 includes substrate 102, nucleation layer 104, thick layer 106, compositionally graded body 108, buffer layer 110, and an active area including a group III-V semicondcutor device in the form of III-nitride heterojunction field-effect transistor (HFET) 112.
As shown in FIG. 1, nucleation layer 104 is formed over substrate 102, thick layer 106 is formed over nucleation layer 104, compositionally graded body 108 is formed over thick layer 106, buffer layer 110 is formed over compositionally graded body 108, and the active area including HFET 112 is formed over buffer layer 110. Nucleation layer 104, thick layer 106, compositionally graded body 108, buffer layer 110, and HFET 112 can each comprise epitaxial layers, grown, for example, using Molecular Beam Epitaxy (MBE). However, other suitable growth methods, such as Hydride Vapor Phase Epitaxy (HVPE), or Metal-Organic Chemical Vapor Deposition (MOCVD), for example, can be used.
In the embodiment shown in FIG. 1, structure 100 comprises a group III-V semiconductor device. More particularly, structure 100 comprises a III-nitride HFET 112. As such, in some embodiments HFET 112 can comprise, for example, a high electron mobility transistor (HEMT). For example, HFET 112 can comprise a heterojunction formed by the interface of an aluminum gallium nitride (AlGaN) region and a gallium nitride (GaN) region (AlGaN/GaN heterojunction not shown in FIG. 1).
Substrate 102 comprises a semiconductor substrate. Substrate 102 has lattice mismatch and differences in thermal expansion characteristics compared to the III-nitride semiconductor material forming HFET 112. In the embodiment shown in FIG. 1, substrate 102 comprises a silicon substrate, for example, a <111> silicon substrate. However, in other embodiments, substrate 102 can comprise other suitable materials such as, for example, sapphire or silicon carbide, such that substrate 102 has lattice mismatch and differences in thermal expansion characteristics compared to the III-nitride or other group III-V semiconductor material of HFET 112. As such, structure 100 includes various layers to compensate for problems introduced when forming HFET 112 over substrate 102. For example, structure 100 includes nucleation layer 104, thick layer 106, compositionally graded body 108, and buffer layer 110.
As shown in FIG. 1, nucleation layer 104 is formed on substrate 102 and allows for growth of a suitable thick layer 106. In structure 100, nucleation layer 104 and thick layer 106 are exemplary and support compositionally graded body 108. In the embodiment shown in FIG. 1, nucleation layer 104 and thick layer 106 each comprise aluminum nitride (AlN). However, in other embodiments, other suitable materials and/or layers can be used as support for compositionally graded body 108.
Also shown in FIG. 1, structure 100 includes compositionally graded body 108. Compositionally graded body 108 can allow for formation of a thick, high quality buffer layer 110 without cracking or even substantial warping. In structure 100, compositionally graded body 108 comprises multiple layers of graded composition. For example, compositionally graded body 108 can comprise layers of AlGaN having varying composition. By controlling the composition and thickness of those layers, compositionally graded body 108 can modulate the stresses applied to substrate 102 in order to minimize or reduce the total stress applied to substrate 102 due to formation of structure 100.
Conventional semiconductor devices typically include regions of decreasing aluminum content to transition the lattice mismatch from substrate 102 to buffer layer 110. The present inventors realize that the conventional approach tends to progressively increase the compressive stress applied to substrate 102 as the aluminum content of the transition layers is reduced. According to the present inventive concepts, however, compositionally graded body 108 includes at least one stress modulating region, which can reverse the net stress applied by that region to substrate 102 so as to apply tensile stress to substrate 102. Thus, compositionally graded body 108 can be configured to modulate the compressive and tensile stresses applied to substrate 102 to avoid the warping and cracking that can result from deformation of substrate 102 due to the accumulated compressive stress in the conventional approach.
Furthermore, compositionally graded body 108 can effectively transition the lattice mismatch between substrate 102 and buffer layer 110. For example, in the embodiment shown in FIG. 1, compositionally graded body 108 can transition lattice mismatch between substrate 102 comprising silicon and buffer layer 110 comprising III-nitride semiconductor material, such that buffer layer 110 can be formed on compositionally graded body 108. By transitioning lattice mismatch between substrate 102 and buffer layer 110, compositionally graded body 108 can deter dislocations in buffer layer 110 and the active group III-V area in which HFET 112 is formed.
FIG. 1 represents buffer layer 110 supporting HFET 112 as comprising AlGaN. While buffer layer 110 can comprise AlGaN, in other embodiments buffer layer 110 can comprise other group III-V semiconductor material, for example, GaN. In structure 100, buffer layer 110 can apply stress to substrate 102. For example, buffer layer 110 can apply additional compressive stress to substrate 102, which can vary with the thickness of buffer layer 110.
In conventional III-nitride semiconductor devices, for example, a continuous buffer layer thicker than approximately 1.3 um can cause a substrate to significantly deform, leading to the undesirable warping and crack described above. Thus, some conventional semiconductor devices include a thick substrate to withstand stress from a thick buffer layer. However, including a thick substrate can substantially increase material and fabrication cost. Other conventional strategies for enabling formation of a thick buffer layer can include a non-continuous buffer layer having layers of varying composition, which can deteriorate device performance, for example by reducing voltage breakdown resistance. However, in an embodiment of the present invention, structure 100 can include a thick buffer layer 110 of substantially continuous composition providing high voltage breakdown resistance, for example, an AlGaN buffer layer of substantially continuous composition, while avoiding the disadvantages associated with thick substrates and the potential for warping and cracking present in the conventional art.
As mentioned above, buffer layer 110 can be used to electrically isolate HFET 112 from substrate 102. For example, increasing the thickness of buffer layer 110 can increase the breakdown voltage of semiconductor device 110. In some embodiments of the present invention, buffer layer 110 can be formed to a thickness of approximately 3 um, or greater, thereby enabling a breakdown voltage for HFET 112 of, for example, 900-1000 volts. Thus, structure 100 can support a high breakdown voltage so as to be suitable for high power applications.
It will be appreciated that structure 100 represents an exemplary group III-V semiconductor device including a compositionally graded body, in accordance with one embodiment of the present invention. As such, other embodiments of the present invention can utilize varying materials and layers. For example, while structure 100 includes aluminum, gallium and nitrogen, other embodiments can also include indium, or other suitable constituents as described in the Definition section above.
Referring now to FIG. 2, FIG. 2 shows a flow chart illustrating a method of fabricating a group semiconductor device including a stress modulating compositionally graded body, according to an embodiment of the present invention. Certain details and features have been left out of flowchart 200 that are apparent to a person of ordinary skill in the art. For example, a step may consist of one or more substeps or may involve specialized equipment or materials, as known in the art. Steps 270 through 276 indicated in flowchart 200 are sufficient to describe an embodiment of the present invention; however, other embodiments of the invention may utilize steps different from those shown in flowchart 200.
It is noted that the processing steps shown in flowchart 200 are performed on a processed wafer, which may also be referred to simply as a wafer or a semiconductor die or simply a die in the present application. Moreover, structures 370 through 376 in FIGS. 3A through 3D illustrate the result of performing steps 270 through 276 of flowchart 200, respectively. For example, structure 370 shows a semiconductor structure after processing step 270, structure 372 shows structure 370 after the processing of step 272, structure 374 shows structure 372 after the processing of step 274, and so forth.
Referring now to step 270 of FIG. 2 and FIG. 3A, step 270 of flowchart 200 comprises providing a substrate under tensile stress by forming an AlN thick layer over an AlN nucleation layer over the substrate. Structure 370 of FIG. 3A shows a cross-sectional view of a structure including a substrate, after completion of step 270 of flowchart 200 in FIG. 2. In structure 370, substrate 302 corresponds to substrate 102, nucleation layer 304 corresponds to nucleation layer 104, and thick layer 306 corresponds to thick layer 106 in FIG. 1. In FIG. 3A, substrate 302 is provided under tensile stress by forming nucleation layer 304 over substrate 302 and thick layer 306 over nucleation layer 304. Thick layer 306 can be formed, for example, by growing AlN in a high temperature process. It will be appreciated that the tensile stress is such that substrate 302 is provided substantially without cracking.
Referring now to step 272 in FIG. 2 and structure 372 in FIG. 3B, at step 272 of flowchart 200, stress region 320 is formed over substrate 302 to apply compressive stress to substrate 302. In structure 372, stress region 320 corresponds to a region of compositionally graded body 108 in FIG. 1, which is at an early stage of formation in structure 372. As shown in FIG. 3B, stress region 320 includes stress layers 322 and 324, which can correspond to respective compositionally graded layers in compositionally graded body 108. Thus, stress layers 322 and 324 can have varying compositions, for example, varying compositions of AlGaN.
As shown in FIG. 3B, in structure 372, stress layer 322 comprises AlxGa1-xN and stress layer 324 comprises AlyGa1-yN, where each of subscripts “x” and “y” represents a different aluminum content in each respective layer. In structure 372, subscript “x” can be less than 1 and greater than 0. Also in structure 372, stress layer 324, formed on stress layer 322, has an aluminum content lower than stress layer 322. As such, in stress layer 324, subscript “y” has a value less than the value of subscript “x,” such that stress region 320 includes layers of decreasing aluminum content. Thus, stress region 320 can apply compressive stress to substrate 302.
In the embodiment of FIG. 3B, substrate 302 is provided to step 272 under tensile stress. By applying compressive stress to substrate 302, stress region 320 can reduce net tensile stress to substrate 302. Furthermore, in some embodiments, stress layer 322 can apply compressive stress to substrate 302 to reduce net tensile stress to substrate 302 and stress layer 324 can apply sufficient additional compressive stress to provide substrate 302 under a net compressive stress upon completion of step 272. The result of step 272 of flowchart 200 is illustrated by structure 372 in FIG. 3B.
Referring now to step 274 in FIG. 2 and structure 374 in FIG. 3C, at step 274 of flowchart 200, stress modulating region 326 is formed over stress region 320 to apply tensile stress to substrate 302. In structure 374, stress modulating region 326 corresponds to a region of compositionally graded body 108 in FIG. 1, which is at an intermediate stage of formation in structure 374. In the embodiment shown in FIG. 3C, stress modulating region 326 comprises stress modulating layer 328, which is formed on stress layer 324 of stress region 320.
In structure 374, stress modulating layer 328 comprises AlGaN having composition AlaGa1-aN where subscript “a” represents the aluminum content in stress modulating layer 328. Notably, stress modulating layer 328 has an aluminum content higher than stress layer 324, such that, stress modulating region 326 applies a tensile stress to substrate 302. As such, subscript “a” can range from a value greater than the value of subscript “y”, to 1. Thus, stress modulating region 328 can apply tensile stress to substrate 302, such that, substrate 302 is provided under, for example, a net tensile stress upon completion of step 274. In one embodiment, the value of subscript “a” may exceed the value of subscript “x” as well as that of subscript “y”. The result of step 274 of flowchart 200 is illustrated by structure 374 in FIG. 3C.
Referring now to step 276 in FIG. 2 and structure 376 in FIG. 3D, at step 276 of flowchart 200, stress region 330 is formed over stress modulating region 326. In structure 372, stress region 330 corresponds to a region of compositionally graded body 308, which, in turn, corresponds to compositionally graded body 108 in FIG. 1. In the embodiment shown in FIG. 3D, stress region 330 comprises stress layer 332 formed on stress modulating layer 328. In structure 376, stress layer 328 comprises AlGaN having composition AlbGa1-bN where subscript “b” represents the aluminum content in stress layer 332. Furthermore, in structure 376, stress layer 332 has an aluminum content lower than stress modulating layer 328, such that, stress region 330 applies a compressive stress to substrate 302. As such, the value of subscript “b” is less than that of subscript “a.” Thus, in some embodiments, stress region 330 can apply a compressive stress to substrate 302 to provide substrate 302 under a reduced net tensile stress upon completion of step 276. The result of step 276 of flowchart 200 is illustrated by structure 376 in FIG. 3D.
Thus, the method illustrated in FIG. 2 and FIGS. 3A through 3D provides for a compositionally graded body including a stress modulating region as part of a group III-V semiconductor device. Additional steps can be performed on structure 376 to fabricate structure 100 in FIG. 1. For example, step 276 of flowchart 200 provides compositionally graded body 308, having a suitable lattice structure such that a buffer layer, for example buffer layer 110 in FIG. 1 can be formed thereon without cracking or significant warping.
As discussed above, the buffer layer can apply compressive stress to the substrate, for example, substrate 302. In conventional semiconductor devices, a thick buffer layer can apply compressive stress to the substrate in addition to the accumulated compressive stress produced by the layers used to transition between the substrate and the buffer layer, resulting in significant warping and/or cracking. However, by including stress modulating region 326, compositionally graded body 308 can modulate the stresses applied to substrate 302 to reduce the net applied stress, thereby reducing the incidence of significant warping and/or cracking. More particularly, stress modulating region 326 can apply tensile stress to substrate 302 compensate for excessive compressive stress applied by a thick buffer layer.
Subsequently, structure 100 can be formed by fabricating HFET 112 on buffer layer 110 and cooling the wafer, which can apply additional tensile stress to substrate 302. Preferably, each layer in structure 100 is controlled to result in a substantially stress free substrate 302 after wafer cooling. For example, by adjusting the thickness and composition of the various semiconductor device layers, the stresses on substrate 302 can be balanced to limit the net stress applied to substrate 302.
It will be appreciated that the method illustrated in FIG. 2 and FIGS. 3A through 3D is merely exemplary and is not intended to limit to the scope of the present invention. For example, while stress region 320 in FIG. 3B comprises stress layer 322 and 324, the number and thickness of stress layers in stress region 320 can be varied to adjust the stress applied to substrate 302. For example, in one embodiment, stress region 320 can comprise a single stress layer. Similarly, the number and thickness of layers in stress modulating region 326 and stress region 330 can be varied. In one embodiment, stress region 330 can be omitted. In another, compositionally graded body 308 can comprise a plurality of stress modulating regions.
Thus, as discussed above, the present invention achieves a group III-V semiconductor device including a compositionally graded body having a least one stress modulating region. By including the stress modulating region, the compositionally graded body can modulate stress applied to a substrate to provide for a thick continuous buffer layer in the semiconductor device without significant warping and/or cracking. Thus, the semiconductor device can have enhanced breakdown voltage, which is particularly desirable in high power semiconductor devices.
From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would appreciate that changes can be made in form and detail without departing from the spirit and the scope of the invention. Thus, the described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.
Patent Application
20120153351
