Patent Application
20110074459
This application claims priority to Chinese Patent Application No. 200910057966.8, filed on Sep. 28, 2009, by inventors Wei Wei Ruan et al., commonly assigned and incorporated in its entirety by reference herein for all purposes.
The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. In particular, the invention provides a method and system for testing the interconnect structures. More particularly, the invention provides a method and device for testing a plurality of electronic attributes of a copper interconnect structure, but it would be recognized that the invention has a much broader range of applicability.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits.
Increasing circuit density has not only improved the complexity and performance of integrated circuits but has also provided lower cost parts to the consumer. An integrated circuit or chip fabrication facility can cost hundreds of millions, or even billions, of U.S. dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of integrated circuits on it. Therefore, by making the individual devices of an integrated circuit smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in integrated fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. Additionally, as devices require faster and faster designs, process including testing limitations exist with certain conventional processes and testing procedures for wafer reliability.
As merely an example, aluminum metal layers have been the choice of material for semiconductor devices as long as such layers have been used in the first integrated circuit device. Aluminum had been the choice since it provides good conductivity and sticks to dielectric materials as well as semiconductor materials.
Most recently, aluminum metal layers have been replaced, in part, by copper interconnects. Copper interconnects have been used with low k dielectric materials to form advanced conventional semiconductor devices. Copper has improved resistance values of aluminum for propagating signals through the copper interconnect at high speeds.
As devices become smaller and demands for integration become greater, limitations in copper and low k dielectric materials include unwanted migration of Cu or other conducting materials into other portions of the integrated circuit. Accordingly, conducting copper features are typically encased within barrier materials such as silicon nitride (SiN), which impede the diffusion of the copper.
Cu dislocation at post-CMP copper surface and SiN cap is one of top killer mechanisms affecting copper backend reliability failures as well as electric failures. One example of such a failure is local bridging of two or multiple metal lines by high temperature operating life (HTOL) stress.
Examples of Cu dislocation triggered by electromigration include copper mass migration, void formation during grain growth, and grain boundary reorganization. Controlling Cu dislocation is a key solution to improve reliability and yield issues due to such related fail modes.
The sudden and catastrophic failure of the device of
Conventionally, separate test structures have been required to identify electromigration that are used for other testing purposes such as identifying absolute voltage breakdown (Vbd) or time dependent dielectric breakdown (TDDB). Such multiple conventional test structures occupy valuable real estate on the chip that is more profitably allocated to active devices.
From the above, it is seen that improved techniques and structures for testing semiconductor devices are desired.
An embodiment of a test structure in accordance with the present invention comprises a first portion and a second portion of a metallization layer, wherein the first and second portions have the shape of a comb and are formed in a recess of an inter-layer dielectric (ILD) formed over a polysilicon heater element and patterned in an interdigitated comb structure. A third portion of the metallization layer comprises a serpentine metal line interposed between the first and second comb portions. Application of force voltages, and detection of sense voltages, at various nodes of the metallization portions allows identification of the following: (1) electromigration of metal in the metallization portions; (2) extrusion of metal from one metallization portion to contact another; (3) breakdown voltage (Vbd) and time dependent dielectric breakdown (TDDB) of the ILD; (4) contamination in the metallization portions with mobile ions; and (5) k valve and drift in k value of the ILD. A bias voltage may be applied to the polysilicon heater to accomplish temperature control during testing.
An embodiment of a test structure, in accordance with the present invention, comprises a polysilicon pad formed on a substrate and a dielectric layer formed on the polysilicon pad. A metallization layer is formed in a recess in the dielectric layer, the metallization layer comprising a first comb portion interdigitated with and electrically isolated from a second comb portion by the dielectric layer.
An embodiment of a method in accordance with the present invention for testing a semiconductor substrate, comprises, providing a test structure comprising a polysilicon pad formed on a substrate, a dielectric layer formed on the polysilicon pad, and a metallization layer formed in a recess in the dielectric layer, the metallization layer comprising a first comb portion interdigitated with a second comb portion and electrically isolated from the second comb portion by the dielectric layer. A voltage is then applied to the first comb portion.
Various additional objects, features and advantages of the present invention can be more fully appreciated with reference to the detailed description and accompanying drawings that follow.
The test structure of
While the conventional test structure of
Like the conventional test structure of
Copper portions 304 and 306 have the shape of a comb, with adjacent projecting portions 304a and 306a oriented substantially parallel to one another. A first end of copper portion 304 includes a sense node S5 and a force node F5. A second end of copper portion 304 includes a sense node S4 and force node F4. A first end of copper portion 306 includes a force node F3.
Third portion 308 of copper metallization layer 302 is formed in a serpentine shape between portions 304 and 306, and in particular between parallel portions 304a and 306a. A first end of third portion 308 includes a force node F1 and a sense node S1. A second end of third portion 308 includes a force node F2 and a sense node S2.
Also unlike the conventional test structure of
The test structure 300 of
Specifically, incorporated herein by reference for all purposes are the following document: EIA/JEDEC Standard EIA/JESD61 (April 1997), entitled “Isothermal Electromigration Test Procedure”. This document describes a standardized test for evaluating electromigration (EM) along the lines of metallization components of interconnect structures. In particular, this test is used to identify electromigration occurring along relatively long metal lines, for example pieces of metallization having a length of 200 m or greater, and typically 800 m or greater. This EM test is performed by applying a force voltage at a force node of a test structure to induce the electromigration, and receiving at a sense node a sense voltage revealing a changed electrical resistance resulting from electromigration of the metal material.
Accordingly, the test structure 300 of
In a second possible operational mode, test structure 300 may be employed to test for extrusion of Cu. Specifically, as shown above in connection with
Accordingly, the test structure 300 of
In a third possible operational mode, test structure 300 may be employed to test for absolute breakdown voltage (Vbd) and/or time dependent dielectric breakdown (TDDB) characteristics of the interconnect structure. Specifically, breakdown voltage of dielectric material present between adjacent interconnect metallization lines is typically determined by applying a force voltage across the test structure, and sensing a sudden change in voltage revealing the unwanted flow of current through the dielectric, indicating a breakdown event. Because breakdown voltage is temperature dependent, conventionally this testing is performed while heating the test structure to over 100° C. in a furnace. Such testing, however, is relatively clumsy, as it requires relocation of the substrate into the furnace, together with establishing electrical connection with the substrate while disposed in the furnace.
Utilizing an embodiment of a test structure in accordance with the present invention, however, Vbd and TDDB may be detected without the need for placing the substrate within a furnace. Specifically, a bias may be applied to the polysilicon heater 310 of the test structure 300, in order to heat the polysilicon and the overlying interconnect structure.
While the interconnect is being heated, a force bias may be applied to node F4 of metallization portion 304, while a sense voltage is detected at sense node S5 of metallization portion 304. A surge in current characteristic of a breakdown in the dielectric layer, can be detected by the accompanying change in sense voltage. Alternatively, the force voltage can be applied from the other end of the metallization line at force node F5, with voltage sensed at node S4.
Still another possible operational mode for the test structure 300 in accordance with the embodiment of the present invention shown in
Such mobile ion exclusion is sometimes unsuccessful, however, and interconnect structures must accordingly be tested for the presence of such mobile ions.
One important test for the presence of mobile ions is the triangular voltage sweeping (TVS) technique. Specifically, TVS involves heating the interconnect structure, typically to a temperature of between about 250-275° C. Then, a positive bias is applied to the interconnect, and a current-voltage sweep from positive to negative bias is performed. The measured current voltage (CV) curve is compared with the capacitance exhibited by the dielectric component of the interconnect, and then integrated over the applied bias. One specification describing the TVS technique are the JEDEC Foundry Process Qualification Guidelines JP001.01, which are incorporated by reference herein for all purposes. In particular, JEDEC guideline JP001.01, §11.2 states in pertinent part:
Inclusion of the polysilicon heater element into the test structure in accordance with embodiments of the present invention, allows the TVS technique to also be conducted directly on the substrate, without the need for an external heating device. Specifically, a current voltage sweep of one or more of the lines of metallization in the test structure, heated by the polysilicon pad, may be employed to detect the presence of mobile ions such as sodium or potassium.
Still another possible use for the test structure 300 in accordance with an embodiment of the present invention of
k=(d*C)/(∈0*A); where:
k=dielectric constant;
d=distance of separation between parallel conductors;
C=capacitance;
A=area of the plates; and
∈0=permittivity of free space.
For embodiments of test structures in accordance with the present invention, the quantities d, A, and ∈0 are all known. A drift in the k value may thus be revealed by a changed capacitance C, which may be detected as a changed sense voltage received from a force voltage applied at a force node of the adjacent pair of metallization lines (either 304 and 308, or 308 and 306).
An absolute k value for the dielectric material of the interconnect structure may also be obtained from test structure 300 as follows. Specifically, a predetermined force bias may be applied to a first metallization line, and the resulting bias sensed on the adjacent metallization line. From the sense voltage measured, the capacitance of the test structure, and in turn the k value of the dielectric layer, can be determined.
While the invention has been described so far in connection with specific examples, it is understood that the present invention is not limited to these particular embodiments, and alternative embodiments are possible. For example, while the above description has focused upon using a test structure to evaluate characteristics of an interconnect structure fabricated from copper, the present invention is not limited to this particular embodiment. In accordance with alternative embodiments, a test structure could employ interconnect metallization comprising aluminum, rather than copper, and remain within the scope of the present invention. Rather than being fabricated utilizing damascene techniques, such an alternative embodiment of a test structure utilizing aluminum metallization could be formed by lithographic techniques.
It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 200910057966.8 | Sep 2009 | CN | national |
