Patent Application
20080026523
The features and advantages of a semiconductor device according to the present invention and further details of a process of fabricating such a semiconductor device in accordance with the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:
A. Overview
A first example embodiment shows a structure and a method of fabrication of a semiconductor device having an etch stop layer (e.g., bottom oxide layer) over a first device region of the substrate that protects underlying transistors and suicide regions from a subsequent etch of a second stressor layer. This can improve the suicide sheet resistance.
Another feature is that two different type stress layers (e.g., one compressive and one tensile) are formed on two regions of a substrate. The stress layer can increase the device performance in the two regions, especially where the two region have different device types (e.g., PFET or NFET). In a preferred embodiment, a compressive layer (e.g., 66) is formed over a NFET device region (e.g., 12) and a tensile stress layer 70 is formed over a PFET device region (e.g., 14).
B. Example Method Embodiment—Dual Stressor Layers with Etch Stop Layer to Protect Transistors
In the non-limiting example shown in
Also referring to
The tensile stressor layer 66 induces a tensile stress on the channel of the NFET device thereby increasing the NFET carrier mobility. The compressive stressor layer 71 induces a compressive stress on the PFET channel thereby increasing the PFET carrier mobility. The stresses on the substrate regions increase the PFET and NFET device performance.
C. First Example Embodiment
The first example embodiment is shown in
This example description will refer to the first region as the NFET region 12 and the second region as the PFET region 14, but the regions obviously can be interchanged and this description is not limiting.
The substrate can be any semiconductor substrate and is preferably a p-doped Silicon wafer. The substrate can include doped wells such as p and n-wells. For example,
We provide a PFET transistor 46 in the PFET region 14 and a NFET transistor 48 in the NFET region 12. The PFET transistor 46 has PFET silicide regions 44. The NFET transistor 48 has NFET silicide region 63.
The PFET transistor 46 can be comprised of a PFET gate dielectric layer 30; a PFET gate electrode 34; a PFET gate silicide layer (or cap layer) 35 over the PFET gate electrode 34; a PFET spacer(s) 3840, PFET source and drain regions 26 adjacent to the gate electrode 34; and PFET silicide regions 44 on the PFET source and drain regions 26 and PFET channel 53.
The NFET transistor 48 can be comprised of a NFET gate dielectric layer 54; a NFET gate electrode 56; a NFET gate silicide layer (or cap layer) 58 over the NFET gate electrode 56; a NFET spacer 6062, NFET source and drain regions 50 adjacent to the NFET gate electrode 56; and NFET silicide regions 63 on the NFET source and drain regions 44 and NFET channel 31.
D. From a Dielectric Stressor Film Comprised of Two or More Dielectric Layers in the in the NFET Region 12 and a First Dielectric Layer in the PFET Region 14
Next we form an etch stop layer and first stressor layer over the substrate surface. The stressor layer can be a dielectric film is comprised of two or more dielectric layers including a first dielectric layer and a stressor layer.
In this example, referring to
This can be formed by first depositing the ONO layer 656667 over the entire substrate and then patterning the NO layers 6667 to remove the NO layers 6667 from the PFET region 14.
For example, referring to
The etch stop layer 65 can be comprised of oxide or SiON and preferably of oxide. The etch stop layer can be comprised of a material that has an etch selectivity to the first stressor layer 66 of preferably greater than 1:4 and more preferably greater than 1:10. The etch stop layer can have a thickness between 20 and 80 angstroms.
The etch stop layer (e.g., bottom oxide layer 65) preferably has an etch selectivity ratio (using a first etchant) to the first stressor layer (e.g., N layer 66) of greater than 1:4 and more preferably greater than 1:10.
The first stressor layer (e.g., middle nitride (tensile stress) layer) 66 is preferably comprised of nitride, SiON or SiC, or other low-k dielectrics (k less than or equal to 3.0). The first stressor layer can be comprised of any material that induces the proper stress on the FET channels. The first stressor layer can be comprised of one or more layers. The first stressor layer preferably has a tensile stress preferably between +0.4 GPa and +2.6 GPa, and can have a thickness between 200 and 1200 angstroms.
The top dielectric (e.g., oxide) layer 67 can have a thickness between 100 and 300 angstroms.
Referring to
We then etch and remove the top oxide layer 67 and the middle nitride layer 66 in the PFET region 14. The etch stops on the bottom oxide layer 65. For example, we can etch the top oxide layer 67 using a etch comprised of CF4/CH2F2. We can etch the stressor layer (e.g, middle nitride) layer 66 using an etch comprised of CF4/CH3F/O2. The etch of the stressor layer 66 can have an etch selectivity to the etch stop layer 65 using the etchant of greater than 1:4 and more preferably greater than 1:10.
A non-limiting advantage of the embodiment is that the bottom oxide layer 65 in the PFET region 14 protects the PFET silicide regions 3644 from the etch of the middle nitride layer 66. This improves silicide region 3644 resistance control.
Then we remove the NFET mask 69.
E. Form a Second Stressor Layer
We can form a stressor layer 71 (e.g., nitride compressive layer) 71 over the bottom oxide layer 65 and the PFET transistor 46 in the PFET region 14 and not in NFET region 12.
For example, referring to
The (compressive) nitride layer 71 can have a compressive stress between −0.4 GPa and −3.6 GPa; and a thickness between 200 and 1200 angstroms. (compressive stress is in −ve Pa while tensile is +ve.)
A compressive layer 71 induces a compressive stress on the substrate in PFET region and more preferably on the channel of the PFET transistor. The stressor layer can be comprised of any suitable material that produces a suitable stress on the substrate. For example, a compressive stressor layer 71 can be formed of SiN, Silicon oxynitride, or SiC.
Referring to
Next, we etch and remove the nitride layer 70 in the NFET regions 12.
As shown in
The bottom oxide layer 65 preferably has a thickness in the PFET region 14 equal to or less than in the NFET region 12.
F. Completing the Devices
As shown in
Next, we form interconnects (e.g., 7678) to contact the PFET transistor 46.
The devices are completed using additional interconnect layers and dielectric layers.
G. Second Embodiment—Change Order of Tensile and Compressive Stressor Layer Formations
Referring to
Referring to
Then nitride layer 71A is formed over the entire substrate surface and then patterned to remove the layer 71A from the NFET region 12. The bottom dielectric layer (e.g., oxide layer) 65A would protect the silicide regions 63 in the NFET region 12 from the nitride etch. This would improve the silicide region 63 sheet resistance uniformity.
Then the NFET stressor layer (e.g., middle nitride layer 66A and the top oxide layer 67A) would be formed over the entire substrate surface, e.g., over the PFET stressor layer (nitride layer) 71A in the PFET region 14 and over the bottom oxide layer 65A in the NFET region 12.
The NFET stressor layer (e.g. middle nitride layer) 66A and the top oxide layer 67A are removed using a patterning process (resist mask then etch) from the PFET region 14.
Subsequent processing (e.g., contacts, interconnects and dielectric layers) can be formed as shown in
H. Non-Limiting Example Embodiments
In the above description numerous specific details are set forth such as flow rates, pressure settings, thicknesses, etc., in order to provide a more thorough understanding of the present invention. Those skilled in the art will realize that power settings, residence times, gas flow rates are equipment specific and will vary from one brand of equipment to another. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these details. In other instances, well known process have not been described in detail in order to not unnecessarily obscure the present invention.
Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word about or approximately preceded the value of the value or range.
Given the variety of embodiments of the present invention just described, the above description and illustrations show not be taken as limiting the scope of the present invention defined by the claims.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. It is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
