Patent Grant
8679970
This application is related to co-pending and co-assigned U.S. patent application Ser. No. 12/034,708, filed Feb. 21, 2008.
The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a reliable conductive contact structure used in contacting an underlying semiconductor device to external components of a semiconductor chip. The present invention also provides a method of fabricating such a reliable conductive contact structure.
A semiconductor device, such as, for example, a field effect transistor, is often formed with both back end of the line (BEOL) contacts to the gate and source/drain regions of the device to turn the device on/off and to allow current to flow through the device, respectively, and a middle of the line (MOL) contact to the body of the device between the source/drain regions to adjust threshold voltage (Vt).
Traditionally, conductive metals, such as tungsten (W) and aluminum (Al) have been deposited (e.g., by chemical vapor deposition (CVD), sputtering, etc.) into patterned openings (i.e., vias), which are present in the dielectric material of the contact (i.e., metallization) structure, to form both MOL and BEOL contacts. Recently, because of its lower electrical resistivity copper and copper alloys, which require plating, have become the preferred metal for filling the contact openings in both BEOL and MOL contact (i.e., metallization) structures.
Unfortunately, as circuit densities are increased, the aspect ratio (i.e., the ratio of height to width) for both BEOL and MOL contact (i.e., metallization) structures has increased and adequate plating of such high aspect ratio contact structures has proven difficult. Specifically, as circuit densities increase and device sizes are scaled, the width of both BEOL and MOL contact (i.e., metallization) structures is decreased; however, the thickness of the dielectric layers in which these contacts are formed has remained the same (i.e., contact or metallization structures with high height to width ratios). For example, circuit designers currently require MOL and BEOL contacts with aspect ratios that are greater 6:1 and oftentimes greater than 10:1. When conventional plating techniques are used to fill these high aspect ratio openings, seams and voids (collectively referred to as a key-hole seam) develop within the contact (i.e., metallization) structure.
As is shown, and since prior plating processes have been used in forming the contact structure, a key-hole seam (represented by reference numeral 26) is present in the prior art contact structure. The presence of the key-hole seam negatively affects contact performance and, as such, the formation of the same in a contact structure should be avoided.
It is further noted that in prior art contact (i.e., metallization) structures such as shown in
In view of the above, there is a need for providing a new and improved high aspect ratio contact structure in which key-hole seam formation is avoided. That is, there is a need for providing a highly reliable high aspect ratio contact structure in which key-hole seam formation within a high aspect ratio opening of the contact structure is eliminated. Also, there is a further need for providing a contact structure in which the conductive metal of the contact structure does not come into direct contact with the underlying conductive material, e.g., a semiconductor alloy of a gate stack or a conductive metal of a lower interconnect level.
The present invention provides a semiconductor structure including a highly reliable high aspect ratio contact structure in which key-hole seam formation is eliminated. The key-hole seam formation is eliminated in the present invention by providing a densified noble metal-containing liner within a high aspect ratio contact opening that is present in a dielectric material. The densified noble metal-containing liner is located atop a diffusion barrier and both those elements separate the conductive material of the inventive contact structure from a conductive material (e.g., a metal semiconductor alloy of a material stack or a conductive metal of a lower interconnect level) of an underlying semiconductor structure.
The densified noble metal-containing liner of the present invention is formed by deposition of a noble metal-containing material having a first density and subjecting the deposited noble metal-containing material to a densification treatment process that increases the first density of the deposited noble metal-containing material to a second, higher density. The densification treatment process employed in the present invention may comprise thermal treatment or plasma treatment. It is further observed that the densified noble metal-containing liner of the present invention has a lower resistivity as compared to the as-deposited noble metal-containing material.
In one aspect, the invention provides a semiconductor structure that comprises:
at least one semiconductor structure located on a surface of a semiconductor substrate, said at least one semiconductor structure including an upper surface that is comprised of a conductive material;
a dielectric material located on said surface of said semiconductor substrate, said dielectric material including a contact opening that extends to the upper surface of said conductive material of said at least one semiconductor structure, and said contact opening having an aspect ratio of greater than 3:1;
a diffusion barrier present within said contact opening, said diffusion barrier lines sidewalls of said contact opening and has a bottom portion that is located atop said upper surface of said conductive material;
a densified noble metal-containing liner present on said diffusion barrier within said contact opening; and
a conductive metal-containing material located atop said densified noble metal-containing liner within said contact opening.
In one embodiment of the inventive structure, the at least one semiconductor structure is a transistor and said conductive material of said at least one semiconductor structure is a metal semiconductor alloy that is located on an upper surface of a material stack of the transistor.
In another embodiment of the inventive structure, the at least one semiconductor structure is an interconnect level and said conductive material of said at least one semiconductor structure is located within a dielectric material.
Notwithstanding the type of semiconductor structure employed, the densified noble metal-containing liner comprises one of Ru, Rh, Ir, Pt, Co, Pd and alloys thereof, the conductive metal-containing material is one of Cu, W, and Al, and the diffusion barrier comprises one of Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, and WN.
In another aspect of the invention, a method of forming a semiconductor structure is provided that comprises:
providing at least one semiconductor structure located on a surface of a semiconductor substrate, said at least one semiconductor structure including at least an upper surface that is comprised of a conductive material;
forming a dielectric material on said surface of said semiconductor substrate, said dielectric material including a contact opening that extends to the upper surface of said conductive material, and said contact opening having an aspect ratio of greater than 3:1;
forming a diffusion barrier at least within said contact opening, said diffusion barrier lining sidewalls of said contact opening and covering said upper surface of said conductive material of said at least one semiconductor structure;
forming a densified noble metal-containing material on said diffusion barrier at least within said contact opening; and
providing a conductive metal-containing layer atop said densified noble metal-containing material at least within said contact opening.
In one embodiment of the inventive method, the at least one semiconductor structure is a transistor and said conductive material of said at least one semiconductor structure is a metal semiconductor alloy that is located on an upper surface of a material stack of the transistor.
In another embodiment of the inventive method, the at least one semiconductor structure is an interconnect level and said conductive material of said at least one semiconductor structure is located within a dielectric material.
Notwithstanding the type of semiconductor structure employed, the densified noble metal-containing material is formed by deposition of a noble metal-containing material and then subjecting the as-deposited noble metal-containing material to a densification treatment via either a plasma process or a thermal process.
The densification treatment used to densify the as-deposited noble metal-containing material is performed in a H2-containing environment. The H2-containing environment may be used alone i.e., neat, or it may be admixed with an inert gas such as, for example, He, Ar, Ne, Kr, Xe, N2 or mixtures thereof. In one preferred embodiment, the environment employed to densify the as-deposited noble metal-containing layer is a H2-containing gas that is mixed with Ar. A preferred ratio is 95% H2 with 5% Ar. The densification process could be done either through a plasma process or a thermal process.
After providing a conductive metal-containing layer, the method of the present invention performs a planarization step that forms a contact structure including a U-shaped diffusion barrier, a U-shaped densified noble metal-containing liner, and a conductive metal-containing layer each of which have an upper surface that is coplanar with an upper surface of the dielectric material.
The present invention, which provides a highly reliable high aspect ratio contact structure and a method of fabricating the same, will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings that accompany the present application are provided for illustrative purposes only, and, as such, these drawings are not drawn to scale.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the invention.
It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
As stated above, the present invention provides a highly reliable high aspect contact structure in which the formation of a key-hole seam within a high aspect ratio contact opening, particularly at an area of the high aspect ratio contact opening that is in close proximity to upper surface of a conductive material of a semiconductor structure, is eliminated.
Reference is now made to
The initial structure 50 of this embodiment of the invention includes a semiconductor substrate 52 having at least one semiconductor structure 54 located thereon. In accordance with the present invention, the at least one semiconductor structure 54 includes a material stack 56 having an upper surface 58 that comprises a metal semiconductor alloy (i.e., a silicide or germanide). It is noted that in the drawings, the one semiconductor structure 54 is depicted as a field effect transistor (FET). Although such a semiconductor structure 54 is depicted and illustrated, the present invention also contemplates other semiconductor structures including, for example, capacitors, diodes, bipolar transistors, BiCMOS devices, memory devices and the like which include a patterned material stack having an upper surface that is comprised of a metal semiconductor alloy or another conductive material such as a metal or metal alloy.
The term “semiconductor substrate” is used throughout this application to denote any semiconducting material including, for example, Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, InP and other III/V or II/VI compound semiconductors. In addition to these listed types of semiconducting materials, the present invention also contemplates cases in which the semiconductor substrate 52 is a layered semiconductor such as, for example, Si/SiGe, Si/SiC, silicon-on-insulators (SOIs) or silicon germanium-on-insulators (SGOIs). In some embodiments of the present invention, it is preferred that the semiconductor substrate 52 be composed of a Si-containing semiconductor material, i.e., a semiconductor material that includes silicon. The semiconductor substrate 52 may be doped, undoped or contain doped and undoped regions therein.
It is also noted that the semiconductor substrate 52 may be strained, unstrained or contain strained regions and unstrained regions therein. The semiconductor substrate 52 may also have a single crystal orientation or alternatively, the substrate 52 may be a hybrid semiconductor substrate that has surface regions having different crystallographic orientations. The semiconductor substrate 52 may also have one or more isolation regions such as, for example, trench isolation regions or field oxide isolation regions, located therein.
Next, the at least one semiconductor structure 54 including a material stack 56 (patterned or non-patterned) having an upper surface 58 that comprises a metal semiconductor alloy is formed. The at least one semiconductor structure 54 is formed utilizing conventional techniques that are well known to those skilled in the art. The processing details may vary depending on the type of structure being fabricating. In the case of a field effect transistor, deposition, lithography, etching and ion implantation can be used in forming the field effect transistor. Alternatively, a replacement gate process can be used in forming the field effect transistor.
In the case of a field effect transistor, the material stack 56 further includes a gate dielectric (not specifically shown or labeled) and an overlying gate conductor (not specifically shown or labeled). The FET also includes at least one spacer 60 located on exposed sidewalls of the material stack 56, and source/drain regions (not specifically shown or labeled) located within the semiconductor substrate 52 at the footprint of the material stack 56. The gate dielectric, the gate conductor and the spacer 60 are comprised of conventional materials. For example, the gate dielectric is comprised of an oxide, nitride, oxynitride or combinations and multilayers thereof. The gate conductor is comprised of polySi, SiGe, an elemental metal, an alloy including an elemental metal, a metal silicide, a metal nitride or any combination including multilayers thereof. The spacer 60, which is optional, is comprised of an oxide, a nitride, an oxynitride or any combination, including multilayers thereof.
The metal semiconductor alloy that is located at the upper surface 58 of material stack 56 is formed utilizing a standard salicidation (‘self-aligned’) process well known in the art. This includes forming a metal capable of reacting with a semiconductor material atop the entire structure, forming a barrier layer atop the metal, heating the structure to form a metal semiconductor alloy, removing non-reacted metal and the barrier layer and, if needed, conducting a second heating step. When a semiconductor material is not present, a layer of a semiconductor-containing material can be formed prior to forming the metal. The second heating step is required in those instances in which the first heating step does not form the lowest resistance phase of the metal semiconductor alloy. The metal used in forming the metal semiconductor alloy comprises one of Ti, Ni, Pt, W, Co, Ir, and the like. Alloying additives can also be present as desired. The heating, i.e., anneal, step used in forming the metal semiconductor alloy includes conditions that are well known to those skilled in the art. It is noted that during the formation of the metal semiconductor alloy layer atop the material stack, a metal semiconductor alloy can be also formed on any exposed surfaces of the semiconductor substrate in which the metal was formed.
The initial structure 50 shown in
The dielectric material 64 may comprise any dielectric used in middle of the line (MOL) and/or back end of the line (BEOL) applications. The dielectric material 64 may be porous or non-porous. Some examples of suitable dielectrics that can be used as the dielectric material 64 include, but are not limited to: SiO2, a doped or undoped silicate glass, C doped oxides (i.e., organosilicates) that include atoms of Si, C, O and H, silsesquioxanes, thermosetting polyarylene ethers, or multilayers thereof, silicon nitride, silicon oxynitride or any combination, including multilayers thereof. The term “polyarylene” is used in this application to denote aryl moieties or inertly substituted aryl moieties which are linked together by bonds, fused rings, or inert linking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl and the like. In one embodiment, the dielectric material 64 is SiO2 that is formed from a TEOS (tetraethylorthosilane) precursor.
The dielectric material 64 typically has a dielectric constant that is about 4.0 or less, with a dielectric constant of about 2.8 or less being even more typical. The thickness of the dielectric material 64 may vary depending upon the dielectric material used. Typically, and for normal MOL and/or BEOL applications, the dielectric material 64 has a thickness from about 200 to about 450 nm.
The contact opening 66 that is present within the dielectric material 64 is formed by lithography and etching. The lithographic process includes forming a photoresist (not shown) atop the dielectric material 64, exposing the photoresist to a desired pattern of radiation and developing the exposed photoresist utilizing a conventional resist developer. The etching process includes a dry etching process (such as, for example, reactive ion etching, ion beam etching, plasma etching or laser ablation), or a wet chemical etching process that selectively removes the exposed dielectric material 64. Typically, reactive ion etching is used in providing the contact opening 66. After etching, the photoresist is typically removed utilizing a conventional resist stripping process well known to those skilled in this art. As shown, the contact opening 66 has sidewalls. The sidewalls within the contact opening 66 may be substantially vertical, as shown, or some tapering may be evident. The contact opening 66 typically has an aspect ratio that is greater than 3, preferably greater than 5, more preferably greater than 10:1. The contact opening 66 may be referred to in the art as a via opening.
After providing the initial structure 50 shown in
The diffusion barrier 68 comprises Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, WN or any other material that can serve as a barrier to prevent a conductive material from diffusing there through. The thickness of the diffusion barrier 68 may vary depending on the deposition process used as well as the material employed. Typically, the diffusion barrier 68 has a thickness from about 2 to about 50 nm, with a thickness from about 5 to about 20 nm being more typical.
The diffusion barrier 68 is formed by a deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, chemical solution deposition and plating.
Next, and as shown in
The noble metal-containing material 70 is formed by a deposition process such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and plasma enhanced atomic layer deposition (PEALD). The precursors and conditions for the deposition, which are well known to those skilled in the art, may vary depending on the exact deposition process used in forming the noble metal-containing material 70.
Next, and as is illustrated in
The densification treatment (either thermal or plasma) is performed in a H2-containing environment. The H2-containing environment may be used neat or it may be admixed with an inert gas such as, for example, He, Ar, Ne, Kr, Xe, N2 or mixtures thereof. In one preferred embodiment, the treatment employed to densify the as-deposited noble metal-containing layer is a H2-containing environment that is mixed with Ar. A preferred ratio is 95% H2 with 5% Ar. The densification process could be done either through a plasma process or a thermal process.
The densification treatment process used to density the as-deposited noble metal-containing material 70 is performed utilizing any conditions in which a hydrogen-containing environment (e.g., gaseous or plasma) can be used to increase the density of the as-deposited noble metal-containing material 70. Typically, the densification treatment employed in the present invention is performed at an elevated temperature that is typically within a range from about 100° to about 500° C., with a temperature from about 150° to about 450° C. being even more typical. The duration of the densification treatment may vary depending on the type of noble metal-containing material being subjected to said treatment. Typically, the duration of the densification treatment is from about 1 to about 20 minutes, with a duration from about 2 to about 5 minutes being even more typical.
As mentioned above, the densification treatment increases the density of the as-deposited noble metal-containing material 70. Moreover, the densification treatment decreases the resistivity of the as-deposited noble metal-containing material 70. With respect to the resistivity of the treated noble metal-containing material 70′, the plasma treated noble metal-containing material 70′ typically has a resistivity below 60 micro-ohm cm for the thickness range mentioned above.
Next, and as shown in
The thickness of the optional seed layer 74 may vary depending on the material of the optional plating seed layer as well as the technique used in forming the same. Typically, the optional plating seed layer 74 has a thickness from about 2 to about 80 nm.
When present, the optional plating seed layer 74 is formed by a conventional deposition process including, for example, CVD, PECVD, ALD, and physical vapor deposition (PVD).
A conductive metal-containing layer 76 is then formed within the opening 66 as well as atop the surface of any of the optional plating seed layer 74 or the treated noble metal-containing material 70′ that extends beyond the opening 66 providing the structure shown in
It is noted that in
After deposition of the conductive metal-containing layer 76, the structure shown in
The contact structure shown in
After providing the at least one semiconductor structure 54′ and forming the dielectric capping layer 84 thereon as shown in the lower portion of
The contact structure shown in
While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
| Number | Name | Date | Kind |
|---|---|---|---|
| 5891513 | Dubin et al. | Apr 1999 | A |
| 6143645 | Hsu et al. | Nov 2000 | A |
| 6399512 | Blosse et al. | Jun 2002 | B1 |
| 6784485 | Cohen et al. | Aug 2004 | B1 |
| 7086138 | Anderson | Aug 2006 | B2 |
| 7112508 | Rhodes et al. | Sep 2006 | B2 |
| 7214602 | Marsh | May 2007 | B2 |
| 7365001 | Yang et al. | Apr 2008 | B2 |
| 7727890 | Edelstein et al. | Jun 2010 | B2 |
| 7951714 | Edelstein et al. | May 2011 | B2 |
| 20020121699 | Cheng et al. | Sep 2002 | A1 |
| 20040203176 | Zhao et al. | Oct 2004 | A1 |
| 20050181598 | Kailasam | Aug 2005 | A1 |
| 20050200024 | Clevenger et al. | Sep 2005 | A1 |
| 20060128150 | Gandikota et al. | Jun 2006 | A1 |
| 20060220248 | Suzuki | Oct 2006 | A1 |
| 20070099422 | Wijekoon et al. | May 2007 | A1 |
| 20070166995 | Malhotra et al. | Jul 2007 | A1 |
| 20070190780 | Chung et al. | Aug 2007 | A1 |
| 20070216031 | Yang et al. | Sep 2007 | A1 |
| 20070259519 | Yang et al. | Nov 2007 | A1 |
| 20080057198 | Yoon et al. | Mar 2008 | A1 |
| 20080230906 | Wong et al. | Sep 2008 | A1 |
| 20080237859 | Ishizaka et al. | Oct 2008 | A1 |
| 20080242088 | Suzuki | Oct 2008 | A1 |
| 20090087981 | Suzuki et al. | Apr 2009 | A1 |
| 20090246952 | Ishizaka et al. | Oct 2009 | A1 |
| Number | Date | Country |
|---|---|---|
| 2349033 | Nov 2002 | CA |
| 2039516 | Jun 2003 | CA |
| WO0004574 | Jan 2000 | WO |
| WO2006016642 | Feb 2006 | WO |
| WO2007099922 | Sep 2007 | WO |
| Entry |
|---|
| Lin, QingHuang, et al., “Symposium B: Materials, Processes, Integration, and Reliability in Advanced Interconnects for Micro- and Nano-Electronics,” Apr. 10-12, 2007, http://www.mrs.org/s—mrs/doc.asp?CID=8697&DID=193960. One Page. |
| Lin, Qinghuang, et al., “Symposium B: Materials, Processes, Integration, and Reliability in Advanced Interconnects for Micro- and Nano-Electronics,” Apr. 10-12, 2007, http://www.mrs.org/s—mrs/doc.asp?CID=8697&DID=193960. |
| U.S. Appl. No. 12/034,708 entitled, “Structure and Process for Metallization in High Aspect Ratio Features,” filed on Feb. 21, 2008, First Named Inventor: Chih-Chao Yang. |
| Supplemental European Search Report dated Oct. 12, 2012 received in a corresponding foreign application. |
| Number | Date | Country | |
|---|---|---|---|
| 20090289365 A1 | Nov 2009 | US |
