A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
1. Technological Field
The present disclosure relates generally to circuit elements and more particularly in one exemplary aspect to inductors or inductive devices having various desirable electrical and/or mechanical properties, and methods of utilizing and manufacturing the same.
2. Description of Related Technology
A myriad of different configurations of inductors and inductive devices are known in the prior art. One common approach to the manufacture of efficient inductors and inductive devices is the use of a magnetically permeable toroidal core. Toroidal cores are very efficient at maintaining the magnetic flux of an inductive device constrained within the core itself. Typically these cores (toroidal or not) are wound with one or more magnet wire windings thereby forming an inductor or an inductive device.
More recently, improved low cost and highly consistent inductive apparatus and methods for manufacturing, and utilizing, the same have been developed. One example of this is disclosed in co-owned and co-pending U.S. patent application Ser. No. 12/876,003 filed Sep. 3, 2010 and entitled “Substrate Inductive Devices and Methods”, the contents of which are incorporated herein by reference in its entirety, discloses a substrate based inductive device which utilizes inserted conductive pins in combination with plated substrates to replace traditional windings disposed around a magnetically permeable core. In some variations this is accomplished without a header disposed between adjacent substrates while alternative variations utilize a header. In another variation, the substrate inductive devices are incorporated into integrated connector modules. However, as the electronics utilized within, for example, integrated connector modules has miniaturized, issues such as Conductive Anodic Filament (CAF) have become major barriers to implementing these substrate inductive devices. CAF occurs in substrates (such as printed circuit boards) when copper filament forms in the laminate dielectric material between two adjacent conductors or plated through-hole vias under an electrical bias. CAF can be a significant source of electrical failures in these substrate inductive devices.
Accordingly, despite the broad variety of substrate inductive device configurations, there is a salient need for substrate inductive devices that are much more resistant to failures such as CAF. Furthermore, ideally such improved substrate inductive devices will be both: (1) low in cost to manufacture; and (2) offer improved electrical performance over prior art devices. Ideally such a solution would not only offer very low manufacturing cost and improved electrical performance for the inductor or inductive device, but also provide greater consistency between devices manufactured in mass production; i.e., by increasing consistency and reliability of performance by limiting opportunities for manufacturing errors of the device while minimizing failure modes such as CAF. Furthermore, methods and apparatus for incorporating improved inductors or inductive devices into integrated connector modules are also needed.
The aforementioned needs are satisfied herein by providing improved substrate inductive device apparatus and methods for manufacturing and using the same.
In a first aspect, a substrate inductive device is disclosed. In one embodiment, the substrate inductive device includes a plurality of substrates, at least one of the substrates including a plurality of chip choke components, the chip choke components allowing for the use of larger toroidal cores than would be possible absent the incorporation of the chip choke components.
In an alternative embodiment, the substrate inductive device includes a plurality of substrates comprising a plurality of ferrite cores, at least one of the substrates including a plurality of chip choke components, the chip choke components configured to reduce the occurrence of conductive anodic filament (CAF) formation.
In a second aspect, a method of manufacturing the aforementioned substrate inductive devices is disclosed. In one embodiment, the method of manufacturing the substrate inductive device includes routing and printing a pair of printed circuit boards; placing a plurality of surface mountable chip chokes on one of the printed circuit boards; placing a plurality of ferrite cores on at least one of the printed circuit boards; and routing a plurality of conductive wires around the plurality of ferrite cores by inserting the conductive wires into a plurality of through hole vias located on the pair of printed circuit boards.
In a third aspect, methods of using the aforementioned substrate inductive devices are disclosed.
In a fourth aspect, a single-port connector which utilizes the aforementioned substrate inductive device is disclosed.
In a fourth aspect, a multi-port connector which utilizes the aforementioned substrate inductive device is disclosed.
In a fifth aspect, a method of manufacturing a single-port connector utilizing the aforementioned substrate inductive device is disclosed.
In a sixth aspect, a method of manufacturing a multi-port connector utilizing the aforementioned substrate inductive device is disclosed.
In a seventh aspect, networking equipment which utilizes the aforementioned multi-port connectors is disclosed.
The features, objectives, and advantages of the disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, wherein:
Reference is now made to the drawings wherein like numerals refer to like parts throughout.
As used herein, the terms “electrical component” and “electronic component” are used interchangeably and refer to components adapted to provide some electrical and/or signal conditioning function, including without limitation inductive reactors (“choke coils”), transformers, filters, transistors, gapped core toroids, inductors (coupled or otherwise), capacitors, resistors, operational amplifiers, and diodes, whether discrete components or integrated circuits, whether alone or in combination.
As used herein, the term “magnetically permeable” refers to any number of materials commonly used for forming inductive cores or similar components, including without limitation various formulations made from ferrite.
As used herein, the term “signal conditioning” or “conditioning” shall be understood to include, but not be limited to, signal voltage transformation, filtering and noise mitigation, signal splitting, impedance control and correction, current limiting, capacitance control, and time delay.
As used herein, the terms “top”, “bottom”, “side”, “up”, “down” and the like merely connote a relative position or geometry of one component to another, and in no way connote an absolute frame of reference or any required orientation. For example, a “top” portion of a component may actually reside below a “bottom” portion when the component is mounted to another device (e.g., to the underside of a PCB).
Overview
The present disclosure provides, inter cilia, improved low cost and highly consistent inductive apparatus and methods for manufacturing, and utilizing, the same.
More specifically, the present disclosure addresses issues with so-called substrate inductive devices such as conductive anodic filament (CAF) that occurs within similar laminate structures (such as a printed circuit board) under certain conditions. These conditions include high humidity, high bias voltage (i.e. a large voltage differential), high-moisture content, surface and resin ionic impurities, glass to resin bond weakness and exposure to high assembly temperatures that can occur, for example, during lead free solder bonding applications.
In embodiments disclosed herein, a substrate inductive device is disclosed which replaces some of the ferrite cores typically seen in prior art designs with so-called chip chokes. For example, in one embodiment, the present disclosure replaces four (4) traditional common mode chokes with surface mountable chip chokes. The chip choices are advantageous in that they take up much less space than prior art ferrite common mode chokes. Accordingly, by incorporating these chip chokes into, for example, the PoE circuit design known in the prior art, the resultant non-chip choke circuitry can accommodate larger ferrite cores, resulting in larger associated via-to-via and via-to-trace spacing, than would otherwise be possible thereby alleviating issues with, for example, CAR In one embodiment, these chip chokes comprise those choke coil devices disclosed in co-owned U.S. Provisional Patent Application Ser. No. 61/732,698 filed Dec. 3, 2012 and entitled “Choke Coil Devices and Methods of Making and Using the Same”, the contents of which are incorporated herein by reference in its entirety. In addition, by incorporating these surface-mountable chip chokes in the underlying magnetic circuit design the number of through hole vias that need to be filled with conductive wires is cut by roughly half thereby improving manufacturing times and cost associated with these substrate inductive devices.
Methods of manufacturing and using the aforementioned substrate inductive devices are also disclosed.
Exemplary Embodiments
Detailed descriptions of the various embodiments and variants of the apparatus and methods of the present disclosure are now provided.
Substrate Inductive Device Apparatus
It is well known in the electronics industry that conductive anodic filament (CAF) occurs within a laminate structure (such as a printed circuit board) under certain conditions. These conditions include high humidity, high bias voltage (i.e. a large voltage differential), high-moisture content, surface and resin ionic impurities, glass to resin bond weakness and exposure to high assembly temperatures that can occur, for example, during lead free solder bonding application. Typically, CAF forms within the laminate, and at the surface from: (1) via-to-via; (2) via-to-trace; (3) trace-to-trace; and (4) layer-to-layer. Within the context of substrate inductive devices, via-to-via CAF formation is particularly problematic. Furthermore, within the context of substrate inductive devices, such as transformers, the bias voltages that can occur between the primary and secondary windings can be particularly problematic for CAF, especially during high-potential events. In the context of magnetic components for use in, for example, router and switch applications, these magnetic components must meet the CAF and high-voltage potential (HiPot) requirements as specified per IEEE/IPC guidelines.
The five (5) ferrite cores are used to make the four (4) transformers 202 and the single PoE choke 206 which serve a similar function as those illustrated in
In one variant of the disclosure, the ferrite cores illustrated in
Accordingly, the circuitry illustrated in the embodiment illustrated in
Methods of Manufacture
Referring now to
At step 304, the surface mountable chip chokes are placed onto the printed circuit board. In one embodiment, the printed circuit board has a screen printable solder paste applied thereto. Upon application of the solder paste, the chip chokes are placed onto the solder paste and the underlying printed circuit board pads. Alternatively, the surface mountable chip chokes can be manually placed onto the printed circuit board without the use of solder paste and can be subsequently hand soldered onto the printed circuit board.
At step 306, the surface mountable chip chokes are soldered to the printed circuit board, either by automated processes such as IR reflow, or by hand soldering the surface mountable chip chokes to the printed circuit board.
At step 308, the ferrite cores are placed onto the printed circuit board. In one embodiment, the ferrite cores are secured to one of the printed circuit boards using an epoxy and subsequently inserted into an assembly fixture. The assembly fixture will maintain a fixed distance between the opposite printed circuit board and the cores so as to accommodate thermal expansion during subsequent soldering operations. The use of spacing to accommodate, inter alia, thermal expansion of the ferrite cores is disclosed in co-owned and co-pending U.S. patent application Ser. No. 12/876,003 filed Sep. 3, 2010 and entitled “Substrate Inductive Devices and Methods”, the contents of which were previously incorporated herein by reference in its entirety.
At step 310, the conductive wires that join the substrates and ultimately form the wires for the underlying magnetic cores are placed within their respective conductive vias and soldered. The placement of conductive wires that join the substrates are also disclosed in co-owned and co-pending U.S. patent application Ser. No. 12/876,003 filed Sep. 3, 2010 and entitled “Substrate Inductive Devices and Methods”, the contents of which were previously incorporated herein by reference in its entirety.
It will be recognized that while certain aspects of the invention are described in terms of specific design examples, these descriptions are only illustrative of the broader methods of the invention, and may be modified as required by the particular design. Certain steps may be rendered unnecessary or optional under certain circumstances. Additionally, certain steps or functionality may be added to the disclosed embodiments, or the order of performance of two or more steps permuted. All such variations are considered to be encompassed within the invention disclosed and claimed herein.
While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the art without departing from the invention. The foregoing description is of the best mode presently contemplated of carrying out the invention. This description is in no way meant to be limiting, but rather should be taken as illustrative of the general principles of the invention. The scope of the invention should be determined with reference to the claims.
This application claims the benefit of priority to co-owned U.S. Provisional Patent Application Ser. No. 61/723,692 of the same title filed Nov. 7, 2012, the contents of which are incorporated herein by reference in its entirety. This application is also related to co-owned and co-pending U.S. patent application Ser. No. 11/985,156 filed Nov. 13, 2007 and entitled “Wire-Less Inductive Devices and Methods” which claims priority to U.S. Provisional Patent Application Ser. No. 60/859,120 filed Nov. 14, 2006 of the same title, the contents of each of the foregoing being incorporated herein by reference in its entirety. This application is also related to co-owned and co-pending U.S. Pat. No. 7,982,572 filed Jul. 15, 2009 and entitled “Substrate Inductive Devices and Methods”, which claims priority to U.S. Provisional Patent Application Ser. No. 61/135,243, filed Jul. 17, 2008 of the same title, the contents of each of the foregoing being incorporated herein by reference in its entirety. Furthermore, this application is also related to co-owned and co-pending U.S. patent application Ser. No. 12/876,003 filed Sep. 3, 2010 and entitled “Substrate Inductive Devices and Methods”, the contents of which are incorporated herein by reference in its entirety.
Number | Date | Country | |
---|---|---|---|
61723692 | Nov 2012 | US |