Patent Application
20240355669
The various aspects and embodiments described herein pertain generally to a substrate processing method and a substrate processing apparatus.
Patent Document 1 discloses a method of manufacturing a semiconductor device by using a SIMOX (Separation by Implanted Oxygen) substrate. According to the disclosure of Patent Document 1, after a layer including a memory element and a field effect transistor with a first single crystalline semiconductor layer as an active layer is formed on one surface of the SIMOX substrate, a second single crystalline semiconductor layer formed on a surface opposite to the one surface is removed by at least one of etching or grinding/polishing.
Non-patent Document 1: Japanese Patent Laid-open Publication No. 2011-097105
Exemplary embodiments provide a technique capable of thinning a first substrate appropriately in a combined substrate in which the first substrate and a second substrate are bonded to each other.
In an exemplary embodiment, a method of processing a combined substrate in which a first substrate and a second substrate are bonded to each other is provided. A device layer including multiple devices is formed on a front surface side of the first substrate. The substrate processing method includes forming a light leakage prevention layer by radiating first laser light to an oxygen-containing film formed between the device layer and a position where a modification layer serving as a starting point for separation of the first substrate is formed; forming the modification layer by radiating second laser light to an inside of the first substrate after the forming of the light leakage prevention layer; and separating the first substrate starting from the modification layer to thin the first substrate.
According to the exemplary embodiment, it is possible to appropriately thin the first substrate in the combined substrate in which the first substrate and the second substrate are bonded to each other.
In a manufacturing process for a semiconductor device, a semiconductor substrate (hereinafter, sometimes referred to as “wafer”) on a surface of which a device layer including a plurality of electronic circuits and the like is formed is thinned. For example, the thinning of the wafer is performed by radiating laser light to an inside of the wafer as a processing target to form a modification layer, and then separating the wafer into a device wafer on a front side and a separation wafer on a rear side, starting from the modification layer.
Recently, for the purpose of improving an efficiency of a semiconductor device (transistor) as a product, a SOI (Silicon on Insulator) substrate in which a single crystalline semiconductor layer (for example, single crystalline silicon) and an insulating layer (for example, SiO2) are stacked may be used. An example of this SOI substrate is the SIMOX substrate described in Patent Document 1. When the SOI substrate is used, it is possible to reduce parasitic capacitance of the transistor, thus increasing an operating speed while reducing power consumption.
However, when using the SOI substrate in this way, it has been difficult to appropriately perform the above-described thinning of the wafer.
Specifically, when the wafer is thinned by etching as described in Patent Document 1, for example, it takes time to thin the wafer, and it is necessary to use a chemical liquid and a gas in large amounts.
Further, when grinding and polishing the wafer as described in Patent Document 1, for example, a large amount of grinding water is required to thin the wafer, and a large amount of grinding debris is generated during the grinding.
Besides, when forming the modification layer inside the wafer as described above, there is a risk that radiated laser light, for example, near infrared (NIR) light may penetrate the single crystalline semiconductor layer and the insulating layer, causing a light leakage to affect the device layer.
Here, as a way to suppress the influence of the light leakage on the device layer, a focus (a position where the modification layer is formed) of the laser light inside the wafer is shifted upwards (to the rear side opposite to the front side where the device layer is formed), the light heading toward the device layer may be defocused. In this case, however, as the formation position of the modification layer is shifted upwards, a position of a separation surface (thinning interface) of the wafer is also shifted upwards, which may cause an increase in a grinding amount of a rear surface of the wafer in a post-process.
In view of the foregoing, exemplary embodiments of the present disclosure provide a technique capable of appropriately thinning a first substrate in a combined substrate in which the first substrate and a second substrate are bonded to each other. Hereinafter, a wafer processing system as a substrate processing apparatus and a wafer processing method as a substrate processing method according to an exemplary embodiment will be described with reference to the accompanying drawings. In the present specification and the drawings, parts having substantially the same functions and configurations will be assigned same reference numerals, and redundant description will be omitted.
A wafer processing system 1 according to the present exemplary embodiment, which will be described later in detail, performs a processing on a combined wafer T as a combined substrate in which a first wafer W as a first substrate and a second wafer S as a second substrate are bonded to each other as shown in
The first wafer W is, for example, a semiconductor wafer such as a silicon substrate. A SiO2 film as an insulating layer is formed on the front surface Wa of the first wafer W. For example, the SiO2 film may be an oxygen-doped silicon layer which is formed as a part of the thickness of the first wafer W is modified by doping of oxygen (O2). A Si film as a single crystalline silicon layer (single crystalline semiconductor layer) and a device layer Dw including a plurality of devices are further formed in the SiO2 film. That is, the first wafer W has a structure as an SOI substrate in which the insulating layer and the single crystalline semiconductor layer are stacked. Further, a surface film Fw is further formed in the device layer Dw, and the first wafer W is bonded to the second wafer S with the surface film Fw therebetween. The surface film Fw may be, by way of non-limiting example, an oxide film (a THOX film, a SiO2 film, or a TEOS film), a SiC film, SiCN film, or an adhesive. Further, a peripheral portion We of the first wafer W is chamfered, and the thickness of the peripheral portion We decreases as it goes toward a leading end thereof when viewed on a cross section thereof.
Furthermore, the SiO2 film formed on the first wafer W does not necessarily need to be the oxygen-doped silicon layer, and may be a general oxide film. The SiO2 film may be formed by modifying an inside of the first wafer W, or may be formed so as to coat an outer surface of the first wafer W. In other words, the first wafer W is provided with the oxygen-containing film.
The second wafer S is, for example, a wafer that supports the first wafer W. A surface film Fs is formed on the second wafer S, and the second wafer S is bonded to the first wafer W with the surface film Fs therebetween. Further, the second wafer S does not need to be the support wafer that supports the first wafer W, and may be, for example, a device wafer having a device layer (not shown) formed on the front surface Sa thereof. In this case, the surface film Fs is formed on the second wafer S with the device layer therebetween.
As shown in
The carry-in/out station 2 is equipped with a cassette placing table 10 configured to place a plurality of, for example, three cassettes C thereon. Further, a wafer transfer device 20 is provided adjacent to the cassette placing table 10 on the negative X-axis side of the cassette placing table 10. The wafer transfer device 20 is configured to be moved on a transfer path 21 extending in the Y-axis direction to transfer the combined wafer T between the cassette C of the cassette placing table 10 and a transition device 30 to be described later.
In the carry-in/out station 2, the transition device 30 configured to deliver the combined wafer T to/from the processing station 3 is disposed on the negative X-axis side of the wafer transfer device 20 to be adjacent to the wafer transfer device 20.
The processing station 3 is equipped with, for example, three processing blocks B1 to B3. The first processing block B1, the second processing block B2, and the third processing block B3 are arranged in this order from the positive X-axis side (carry-in/out station 2 side) toward the negative X-axis side.
The first processing block B1 includes an etching device 40 configured to etch a ground surface of the first wafer W ground in a processing device 80 to be described later, a cleaning device 41 configured to clean the ground surface of the first wafer W, and a wafer transfer device 50. The etching device 40 and the cleaning device 41 are stacked on top of each other. Here, the number and the layout of the etching device 40 and the cleaning device 41 are not limited to the shown example.
The wafer transfer device 50 is disposed on the negative X-axis side of the transition device 30. The wafer transfer device 50 has, for example, two transfer arms 51 each configured to hold and transfer the combined wafer T. Each transfer arm 51 is configured to be movable in a horizontal direction and a vertical direction and pivotable around a horizontal axis and a vertical axis. The wafer transfer device 50 is configured to be able to transfer the combined wafer T or the like to the transition device 30, the etching device 40, the cleaning device 41, an interface modifying device 60 to be described later, an internal modifying device 61 to be described later, and a separating device 62 to be described later.
The second processing block B2 is equipped with the interface modifying device 60 configured to form a light leakage prevention layer to be described later, the internal modifying device 61 configured to form a separation surface modification layer that serves as a starting point for separation of the first wafer W, the separating device 62 configured to separate the first wafer W, and a wafer transfer device 70. The interface modifying device 60, the internal modifying device 61, and the separating device 62 are stacked on top of each other. Here, the number and the layout of the interface modifying device 60, the internal modifying device 61, and the separating device 62 are not limited to the shown example. For instance, instead of stacking the interface modifying device 60, the internal modifying device 61 and the separating device 62, at least one of them may be arranged adjacent to another in a horizontal direction.
The interface modifying device 60 as a first laser light radiator is configured to radiate laser light L1 for interface (for example, a CO2 laser) as first laser light to the SiO2 film as the insulating layer formed on the first wafer W, for example. As an example, the laser light L1 for interface has a wavelength equal to or larger than 5 μm, desirably, 9 μm to 10 μm. In the interface modifying device 60, the Si film positioned at a converging point of the laser light L1 for interface is modified to form a light leakage prevention layer M1 serving to suppress transmission of laser light L2 for inside to be described later.
As depicted in
The chuck 100 is supported on a slider table 102 with an air bearing 101 therebetween. A rotating mechanism 103 is provided on a bottom surface of the slider table 102. The rotating mechanism 103 has therein, for example, a motor as a driving source. The chuck 100 is configured to be rotatable around a 0 axis (vertical axis) by the rotating mechanism 103 via the air bearing 101. The slider table 102 is configured to be movable along a rail 105 extending in the Y-axis direction by a horizontally moving mechanism 104 provided on a lower surface thereof. The rail 105 is provided on a base 106. Further, although not particularly limited, a driving source of the horizontally moving mechanism 104 may be, by way of example, a linear motor.
Above the chuck 100, there is provided a laser radiation system 110. The laser radiation system 110 has a laser head 111 and a lens 112. The lens 112 may be configured to be movable up and down by an elevating mechanism (not shown).
The laser head 111 has a laser oscillator (not shown) configured to oscillate laser light in a pulse shape. That is, the laser light radiated from the laser radiation system 110 to the combined wafer T held by the chuck 100 is a so-called pulse laser, and its power is repeated between 0 (zero) and a maximum value. Further, the laser head 111 may have other devices, such as an amplifier.
The lens 112 is a cylindrical member, and is configured to radiate the laser light L1 for interface to the combined wafer T held by the chuck 100.
The internal modifying device 61 as a second laser light radiator is configured to radiate the laser light L2 for inside (for example, NIR light such as a YAG laser) as second laser light to an inside of the first wafer W. The laser light L2 for inside has a wavelength of, e.g. 1 μm to 1.5 μm. In the internal modifying device 61, the first wafer W positioned at a converging point of the laser light L2 for inside is modified to form an internal modification layer M2 serving as a starting point for separation of the first wafer W.
The internal modifying device 61 has the same configuration as the interface modifying device 60. That is, as shown in
The separating device 62 as a separator is configured to separate the first wafer W into a device wafer Wd1 and a separation wafer Wd2, starting from the internal modification layer M2 formed in the internal modifying device 61.
As illustrated in
The wafer transfer device 70 is disposed on the positive Y-axis side of the interface modifying device 60 and the internal modifying device 61, for example. The wafer transfer device 70 has, for example, two transfer arms 71 each configured to transfer the combined wafer T while attracting and holding the combined wafer T with a non-illustrated attracting/holding surface thereof. Each transfer arm 71 is supported by a multi-joint arm member 72, and is configured to be movable in a horizontal direction and a vertical direction and pivotable around a horizontal axis and a vertical axis. Also, the wafer transfer device 70 is configured to be able to transfer the combined wafer T and the like to the etching device 40, the cleaning device 41, the interface modifying device 60, the internal modifying device 61, the separating device 62, and the processing device 80 to be described later.
The processing device 80 is provided in the third processing block B3.
The processing device 80 has a rotary table 81. The rotary table 81 is configured to be rotatable about a vertical rotation center line 82 by a rotating mechanism (not shown). The two chucks 83 configured to attract and hold the combined wafer T is provided on the rotary table 81. The chucks 83 are evenly arranged on the same circumference as the rotary table 81. The two chucks 83 are configured to be moved to a delivery position A0 and a processing position A1 as the rotary table 81 is rotated. Further, each of the two chucks 83 is configured to be rotatable around a vertical axis by a rotating mechanism (not shown).
At the delivery position A0, a delivery of the combined wafer T is performed. A grinding device 84 is disposed at the processing position A1, and grinds the first wafer W while attracting and holding the second wafer S with the chuck 83. The grinding device 84 has a grinder 85 equipped with a grinding whetstone (not shown) configured to be rotatable in an annular shape. Additionally, the grinder 85 is configured to be movable in a vertical direction along a supporting column 86.
The above-described wafer processing system 1 has a control device 90. The control device 90 is, for example, a computer equipped with a CPU, a memory, and the like, and has a program storage (not shown). The program storage stores therein a program for controlling a processing of the combined wafer T in the wafer processing system 1. The program may have been recorded on a computer-readable recording medium H, and may be installed from the recording medium H into the control device 90.
Now, a wafer processing performed by using the wafer processing system 1 will be explained. Further, in the present exemplary embodiment, the combined wafer T is previously formed in a bonding device (not shown) outside the wafer processing system 1.
Furthermore, in the combined wafer T as a processing target according to the present exemplary embodiment, a SiO2 film, a Si film, the device layer Dw, and the surface film Fw are stacked on the front surface Wa of the first wafer W, as shown in
First, the cassette T accommodating therein a plurality of combined wafers T is placed on the cassette placing table 10 of the carry-in/out station 2. Then, the combined wafer T is taken out from the cassette C by the wafer transfer device 20, and transferred to the transition device 30. The combined wafer T transferred to the transition device 30 is then transferred to the interface modifying device 60 by the wafer transfer device 50.
In the interface modifying device 60, the laser light L1 for interface is radiated to the SiO2 film formed on the first wafer W, as shown in
As an example, in the present exemplary embodiment, the temperature of the SiO2 film is increased due to the absorption of the laser light L1 for interface (CO2 laser), so that the temperature of the silicon constituting the first wafer W is increased, whereby a light absorption rate of the silicon is improved. Accordingly, the silicon absorbs the wavelength of the laser light L1 for interface (CO2 laser), and is thus modified to form the light leakage prevention layer M1. In other words, the “modification” of the SiO2 film in the interface modifying device 60 in the present exemplary embodiment includes the modification of the silicon constituting the first wafer W.
The combined wafer T having the light leakage prevention layer M1 formed therein is then transferred to the internal modifying device 61 by the wafer transfer device 50. In the internal modifying device 61, the internal modification layer M2 is formed inside the first wafer W (process P2 of
In the formation of the internal modification layer M2, the laser light L2 for inside is periodically radiated from the laser radiation system 210 while rotating the combined wafer T (first wafer W), and, also, the radiation position of the laser light is moved inwards in a radial direction of the first wafer W. As a result, inside the first wafer W, the internal modification layer M2, which has a substantially spiral shape or concentric circle shape when viewed from the top, is formed in the entire surface of the first wafer W along a plane direction thereof. Here, the formation interval of the internal modification layer M2 in the radial direction may be set as required.
In addition, in forming the internal modification layer M2, by scanning and moving the radiation position of the laser light in a horizontal direction relative to the combined wafer T (first wafer W), the internal modification layer M2 may be formed in an approximately straight line shape.
Further, inside the first wafer W, a crack C2 develops along the formation direction of the internal modification layer M2, that is, along the plane direction of the first wafer W, as illustrated in
Here, the laser light L2 for inside radiated when forming the internal modification layer M2 is NIR light, and has transparency to silicon (Si). For this reason, there is a risk that some of the laser light L2 for inside radiated to the inside of the first wafer W may leak from the converging point (the position where the internal modification layer M2 is formed) and penetrate SiO2 film to affect the device layer Dw.
In this regard, in the present exemplary embodiment, the light leakage prevention layer M1 is formed in the interface modifying device 60 prior to the formation of the internal modification layer M2. The formed light leakage prevention layer M1 absorbs or scatters a leak of the laser light L2 for inside (NIR light), so that the light leakage reaching the device layer Dw can be reduced, and the device layer Dw can be suppressed from being affected by the light leakage.
In addition, it is desirable that a lower end of the internal modification layer M2 formed inside the first wafer W is located above a target thickness (indicated by a dashed line in
The combined wafer T having the internal modification layer M2 formed therein is then transferred to the separating device 62 by the wafer transfer device 50.
In the separating device 62, starting from the internal modification layer M2 and the crack C2, the first wafer W is separated into the device wafer Wd1 on the front surface Wa side and the separation wafer Wd2 on the rear surface Wb side (process P3 of
In the separation of the first wafer W in the process P3, the first wafer W is attracted to and held by the attracting/holding surface of the separating arm 131, and the second wafer S is attracted to and held by the chuck 130 (see
In addition, although the separation of the first wafer W is performed by using the separating arm 131 in the separating device 62 in the present exemplary embodiment, the separation of the first wafer W may be performed when the combined wafer T is transferred from the wafer transfer device 70 to the chuck 83 in the processing device 80. In this case, the processing device 80 functions as a “separator” according to the technique of the present disclosure.
The separation wafer Wd2 separated from the first wafer W is collected to the outside of the wafer processing system 1, for example. As another example, a collector (not shown) may be provided within a moving range of the transfer arm 71, and the separation wafer Wd2 may be collected by this collector.
The combined wafer T after being subjected to the separation of the first wafer W is then transferred to the chuck 83 of the processing device 80 by the wafer transfer device 70. Next, the chuck 83 is moved to the processing position A1, and the separation surface of the device wafer Wd1 is ground by the grinding device 84 (process P4 of
At this time, as stated above, since the internal modification layer M2 is formed with its lower end located above the target thickness (height position of the final thickness) of the first wafer W after being ground, the internal modification layer M2 remaining on the separation surface can be appropriately removed by the grinding.
The combined wafer T in which the first wafer W is thinned to the target thickness in the processing device 80 is then transferred to the cleaning device 41 by the wafer transfer device 70, and the ground surface of the device wafer Wd1 is cleaned (process P5 of
Subsequently, the combined wafer T is transferred to the etching device 40 by the wafer transfer device 50, and the ground surface of the device wafer Wd1 is wet-etched by a chemical liquid (process P6 of
Thereafter, the combined wafer T after being subjected to all the required processes is transferred to the transition device 30 by the wafer transfer device 50, and then transferred to the cassette C on the cassette placing table 10 by the wafer transfer device 20. In this way, the series of processes of the wafer processing in the wafer processing system 1 are completed.
Furthermore, the combined wafer T after being subjected to all the required processes may be further subjected to a CMP (Chemical Mechanical Polishing) processing to flatten the ground surface. This CMP processing may be performed outside or inside the wafer processing system 1. When performing the CMP processing inside the wafer processing system 1, a CMP device configured to perform the CMP processing may be stacked with the etching device 40 and the cleaning device 41 in the first processing block B1, for example.
According to the above-described exemplary embodiment, prior to forming the internal modification layer M2, the SiO2 film provided between the first wafer W and the device layer Dw is modified to form the light leakage prevention layer M1 configured to absorb or scatter the light leakage of the laser light L2 for inside. Accordingly, even if the laser light L2 for inside (NIR light) having transmittance to silicon is radiated in forming the internal modification layer M2, the light leakage of the laser light L2 for inside is suppressed from reaching the device layer Dw, so that any influence on the device layer Dw may be suppressed.
Further, according to the above-described exemplary embodiment, by forming the light leakage prevention layer M1 in this way, the position of the light converging point inside the first wafer W (the position where the internal modification layer M2 is formed) can be brought closer to the device layer Dw. Thus, a grinding amount in the grinding processing (process P4) as a post-process can be reduced.
Specifically, the amount of the laser light L2 for inside transmitted to the device layer Dw when forming the internal modification layer M2 increases as the position of the converging point of the laser light L2 for inside approaches the device layer Dw. In this regard, in the present exemplary embodiment, even when the position of the converging point of the laser light L2 for inside (the formation position of the internal modification layer M2) is brought close to the device layer Dw, the light leakage that is about to be transmitted to the device layer Dw can be absorbed and scattered by the light leakage prevention layer M1. Therefore, the position of the converging point of the laser light L2 for inside can be brought close to the device layer Dw (more specifically, the position of the target thickness in the grinding processing), so the grinding amount in the grinding processing (process P4) can be reduced.
Further, in the above-described exemplary embodiment, although the combined wafer T obtained after the first wafer W is separated is subjected to the grinding processing (process P4), the cleaning of the ground surface (process P5), and the wet etching processing (process S6) in sequence, the grinding processing on the combined wafer T can be appropriately omitted when the position of the converging point of the laser light L2 for inside can be brought close enough to the device layer Dw as described above. That is, although the grinding processing in the above-described process P4 is aimed at reducing the device wafer Wd1 to the required target thickness, the grinding processing of the process P4 can be omitted if the internal modification layer M2 can be formed near the required target thickness position and the first wafer W can be separated near the target thickness position.
In this case, the internal modification layer M2 remaining on the separation surface of the device wafer Wd1 can be removed by the wet etching processing that is performed on the combined wafer T without performing the grinding processing. Further, in this wet etching processing, the separation surface of the combined wafer T is flattened.
In addition, the separation surface of the combined wafer T that has been flattened by the wet etching processing may be further smoothed by the CMP processing as stated above.
Moreover, in the above-described exemplary embodiment, the crack C2 developing in the plane direction from the internal modification layer M2 is made to reach an outer peripheral end of the first wafer W, as illustrated in
In view of this, in the wafer processing system 1 according to the present exemplary embodiment, in order to suppress the formation of this knife edge shape at the peripheral portion We, the peripheral portion We of the first wafer W may be removed as one body with the separation wafer Wd2 (so-called edge trimming). That is, the processing device 80 or the separating device 62 serving to separate the first wafer W may function as a periphery removing device configured to remove the peripheral portion We of the first wafer W.
Specifically, as shown in
Once the light leakage prevention layer M1 is formed, the focal position of the laser light L1 for interface (CO2 laser) is changed to the device layer Dw or the surface film Fw (in the shown example, the surface film Fw) at the peripheral portion We of the first wafer W, as shown in
Once the non-bonding region Ae is formed, the internal modification layer M2 and a peripheral modification layer M3 are sequentially formed in the internal modifying device 61, as shown in
Then, as shown in
In the example shown in
Furthermore, although the light leakage prevention layer M1 and the non-bonding region Ae are formed in this order in the example shown in
In addition, although the exemplary embodiment shown in
Hereinafter, a description will be provided for a case where the combined wafer T has the first wafer W in which an oxygen-doped silicon layer as the SiO2 film is formed.
To form the oxygen-doped silicon layer in the first wafer W, first, a high-concentration of oxygen (O) ions are implanted near the front surface Wa of the first wafer W, as shown in
Further, the way to form the SiO2 layer in the first wafer W is not limited to the above-describe example. By way of example, instead of implanting the high-concentration oxygen ions, a high concentration of carbon (C) ions may be implanted near the front surface Wa of the first wafer W, and the first wafer W having the carbon ions implanted therein is subjected to a heat treatment (annealing processing) at a high temperature to form an oxygen precipitation layer.
Once the SiO2 layer is formed inside the first wafer W, the device layer Dw and the surface film Fw are sequentially formed on the front surface Wa side of the first wafer W, as shown in
Next, as shown in
The combined wafer T formed as described above is then brought into the wafer processing system 1. The combined wafer T brought into the wafer processing system 1 is first transferred to the interface modifying device 60 and, as shown in
Next, the combined wafer T having the light leakage prevention layer M1 formed therein is transferred to the internal modifying device 61. As shown in
At this time, since the light leakage prevention layer M1 is formed between the device layer Dw and the formation position of the internal modification layer M2 within the combined wafer T, it is possible to appropriately suppress the device layer Dw from being affected by a light leakage in the radiation of the laser light L2 for inside. Further, since the light leakage prevention layer M1 is formed in this way, the formation position of the internal modification layer M2 (the position of the converging point of the laser light L2 for inside) can be brought close to the device layer Dw, as illustrated in
The combined wafer T having the internal modification layer M2 formed therein is then transferred to the separating device 62. In the separating device 62, as illustrated in
Here, in the combined wafer T according to the present exemplary embodiment, the formation position of the internal modification layer M2 (the position of the converging point of the laser light L2 for inside) may be brought close to the device layer Dw. In other words, in the processing device 80, the grinding amount of the first wafer W after being separated can be reduced or eliminated.
Thus, in the present exemplary embodiment, the device wafer Wd1 after being separated from the first wafer W is transferred not to the processing device 80 but to the etching device 40. That is, in the present exemplary embodiment, an etching processing (removal of the internal modification layer M2 and flattening) may be performed on the separation surface of the combined wafer T (device wafer Wd1) after being thinned by the separation, as illustrated in
In addition, in this etching processing, the SiO2 layer and the light leakage prevention layer M1 formed inside the first wafer W may be further removed, as shown in
Afterwards, the combined wafer T after being subjected to all the required processes is taken out from the wafer processing system 1. In this way, the series of processes of the wafer processing in the wafer processing system 1 are completed.
In addition, the combined wafer T after being subjected to all the required processes may be further subjected to a CMP processing (smoothing processing) inside or outside the wafer processing system 1.
As stated above, the structure of the combined wafer T to be processed in the wafer processing system 1 is not particularly limited, and the SiO2 film as the oxygen-containing film may be formed on the front surface Wa of the first wafer W, or the SiO2 layer as the oxygen-containing film may be formed inside the first wafer W.
In any case, by forming the light leakage prevention layer M1 prior to the formation of the internal modification layer M2 inside the first wafer W, the device layer Dw can be appropriately prevented or suppressed from being affected by the light leakage.
Further, in the example shown in
Moreover, in the above-described exemplary embodiment, although the interface modifying device 60 configured to form the light leakage prevention layer M1 and the internal modifying device 61 configured to form the internal modification layer M2 (and the peripheral modification layer M3) are arranged independently, these laser radiating devices may be configured as one body.
That is, as shown in
At this time, the one laser radiating system 161 and the other laser radiating system 162 may be arranged independently as shown in
In addition, when the interface modifying device 60 and the internal modifying device 61 are integrated in this way, the radiation of the laser light L1 for interface to the SiO2 film and the radiation of the laser light L2 for inside to the inside of the first wafer W may be performed simultaneously.
More specifically, the laser light L1 for interface is radiated to the SiO2 film while moving the lens 161b, and the laser light L2 for inside is radiated while moving the lens 162b to catch up with the radiation of the laser light L1 for interface to the SiO2 film. That is, in the above-described exemplary embodiment, the internal modification layer M2 is formed after the light leakage prevention layer M1 is formed on the entire surface of the first wafer W. However, the laser light L2 for inside may be radiated to a position corresponding to the light leakage prevention layer M1 immediately after the light leakage prevention layer M1 is formed.
In this case, it is desirable that an output of the laser light L2 for inside or a relative distance between a radiation axis of the laser light L1 for interface and a radiation axis of the laser light L2 for inside is controlled such that the crack C2 that develops when forming the internal modification layer M2 should not reach a position directly below where the laser light L1 for interface is radiated.
Thus, since the formation of the light leakage prevention layer M1 and the formation of the internal modification layer M2 can be performed approximately at the same time as stated above, the time required for the series of processes for the combined wafer T in the wafer processing system 1 can be significantly shortened.
In addition, although the above exemplary embodiment has been described for the example where the laser light L1 for interface is the CO2 laser and the laser light L2 for inside is the NIR light, the kind of the laser light is not particularly limited as long as the light leakage prevention layer M1 and the internal modification layer M2 can be formed appropriately.
In addition, although the above exemplary embodiment has been described for the example where the wafer as a processing target is the SIO wafer (for example, a SIMOX wafer), the structure of the wafer is not particularly limited.
It should be noted that the above-described exemplary embodiment is illustrative in all aspects and is not anyway limiting. The above-described exemplary embodiment may be omitted, replaced and modified in various ways without departing from the scope and the spirit of claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-145022 | Sep 2021 | JP | national |
| 2021-200094 | Dec 2021 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2022/032169 | 8/26/2022 | WO |
