The present disclosure relates generally to substrate processing systems and more particularly to substrate supports with multilayer structure including coupled heater zones with local thermal control.
The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A substrate processing system typically includes several processing chambers (also called process modules) to perform deposition, etching, and other treatments of substrates such as semiconductor wafers. Examples of processes that may be performed on a substrate include, but are not limited to, plasma enhanced chemical vapor deposition (PECVD), chemically enhanced plasma vapor deposition (CEPVD), sputtering physical vapor deposition (PVD), atomic layer deposition (ALD), and plasma enhanced ALD (PEALD). Additional examples of processes that may be performed on a substrate include, but are not limited to, etching (e.g., chemical etching, plasma etching, reactive ion etching, etc.) and cleaning processes.
During processing, a substrate is arranged on a substrate support assembly such as a pedestal or an electrostatic chuck (ESC) arranged in a processing chamber of the substrate processing system. A robot typically transfers substrates from one processing chamber to another in a sequence in which the substrates are to be processed. During deposition, gas mixtures including one or more precursors are introduced into the processing chamber, and plasma is struck to activate chemical reactions. During etching, gas mixtures including etch gases are introduced into the processing chamber, and plasma is struck to activate chemical reactions. The processing chambers are periodically cleaned by supplying a cleaning gas into the processing chamber and striking plasma.
A substrate support assembly for supporting a substrate comprises a baseplate, a ceramic plate arranged on the baseplate, and N resistive heaters arranged in X rows and Y columns and coupled to the ceramic plate. X, Y, and N are integers greater than 1, and N is less than or equal to X*Y. Each of the N resistive heaters have a first terminal and a second terminal. The ceramic plate includes Y conductors arranged in a first layer of the ceramic plate, and X conductors arranged in a second layer of the ceramic plate. The first terminals of each resistive heater in one of the X rows are directly connected to the Y conductors, respectively, by first vias. Second terminals of each resistive heater in the one of the X rows are directly connected to one of the X conductors by second vias.
In another feature, the N resistive heaters are electrically insulated from the baseplate and are arranged at the bottom of the ceramic plate between the baseplate and the ceramic plate.
In another feature, the N resistive heaters are arranged in a third layer of the ceramic plate.
In another feature, the substrate support assembly further comprises a controller configured to connect one of the Y conductors to a power supply, and to connect one of the X conductors to a reference potential.
In another feature, the substrate support assembly further comprises a controller configured to connect the Y conductors to a power supply and the X conductors to a reference potential in a sequence by connecting one of the Y conductors to the power supply and connecting one of the X conductors to the reference potential at a time.
In another feature, the sequence is based on a temperature profile for processing the substrate.
In another feature, the substrate support assembly further comprises a controller configured to connect a first one of the Y conductors to a power supply for a first time period, to connect a first one of the X conductors to a reference potential for the first time period, to disconnect the first one of the Y conductors from the power supply after the first time period, and to connect a second one of the Y conductors to the power supply for a second time period.
In another feature, the substrate support assembly further comprises a controller configured to connect a first one of the Y conductors to a power supply for a first time period, to connect a first one of the X conductors to a reference potential for the first time period, to disconnect the first one of the X conductors from the reference potential after the first time period, and to connect a second one of the X conductors to the reference potential for a second time period.
In another feature, the substrate support assembly further comprises a controller configured to connect a first one of the Y conductors to a power supply for a first time period, to connect a first one of the X conductors to a reference potential for the first time period, to disconnect the first one of the Y conductors from the power supply after the first time period, to disconnect the first one of the X conductors from the reference potential after the first time period, to connect a second one of the Y conductors to the power supply for a second time period, and to connect a second one of the X conductors to the reference potential for the second time period.
In another feature, the second layer is adjacent to the baseplate, and the first layer is arranged on the second layer.
In another feature, the second layer is adjacent to the baseplate, the first layer is arranged on the second layer, and the third layer is arranged on the first layer.
In another feature, the first, second, and third layers are arranged in any order.
In another feature, the substrate support assembly further comprises one or more additional heaters arranged in a third layer of the ceramic plate. The third layer is arranged above or below the first and second layers.
In another feature, the substrate support assembly further comprises one or more additional heaters arranged in a fourth layer of the ceramic plate. The fourth layer is arranged above or below the first, second, and third layers.
In another feature, the substrate support assembly further comprises a clamping electrode and one or more additional heaters arranged in a third layer of the ceramic plate. The third layer is arranged above the first and second layers.
In other features, the substrate support assembly further comprises a clamping electrode arranged in a third layer of the ceramic plate. The third layer is arranged above the first and second layers. The substrate support assembly further comprises one or more additional heaters arranged in a fourth layer of the ceramic plate. The fourth layer is arranged below the first and second layers.
In another features, the substrate support assembly further comprises a clamping electrode and one or more additional heaters arranged in a fourth layer of the ceramic plate. The fourth layer is arranged above the first, second, and third layers.
In other features, the substrate support assembly further comprises a clamping electrode arranged in a fourth layer of the ceramic plate. The fourth layer is arranged above the first, second, and third layers. The substrate support assembly further comprises one or more additional heaters arranged in a fifth layer of the ceramic plate. The fifth layer is arranged below the first, second, and third layers.
In another feature, the substrate support assembly further comprises an adhesive layer arranged between the baseplate and the ceramic plate.
In another feature, the baseplate includes channels for flowing a coolant through the baseplate.
In other features, a system comprises the substrate support assembly, a power supply configured to supply a first DC voltage, and a controller. The controller is configured to sequentially apply the first DC voltage across the X and Y conductors by connecting one pair of the X and Y conductors at a time to the power supply and a reference potential.
In another feature, a sequence for sequentially applying the first DC voltage across the X and Y conductors is based on a temperature profile for processing the substrate.
In other features, the substrate support assembly further comprises one or more additional heaters arranged in a third layer of the ceramic plate, wherein the third layer is arranged above or below the first and second layers. The power supply is configured to supply a second DC voltage. The controller is configured to supply the second DC voltage to the one or more additional heaters.
In other features, a system comprises the substrate support assembly, a power supply configured to supply a first DC voltage, and a controller. The controller is configured to sequentially apply the first DC voltage across the X and Y conductors by connecting one pair of the X and Y conductors at a time to the power supply and a reference potential.
In another feature, a sequence for sequentially applying the first DC voltage across the X and Y conductors is based on a temperature profile for processing the substrate.
In other features, the substrate support assembly further comprises one or more additional heaters arranged in a fourth layer of the ceramic plate. The fourth layer is arranged above or below the first, second, and third layers. The power supply is configured to supply a second DC voltage. The controller is configured to supply the second DC voltage to the one or more additional heaters.
Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.
The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:
In the drawings, reference numbers may be reused to identify similar and/or identical elements.
Substrate supports include heaters to heat substrates during processing. The heaters are controlled to maintain desired temperature profiles across the substrates. Some substrate supports include an array of heaters (e.g., resistive heaters) and switches (e.g., diodes). The heaters in the array are independently operated by controlling the switches. While one of the heaters in the array is turned on and emits heat, all other heaters in the array that are not selected are turned off and do not emit heat. While such a heater array provides a more localized heat output, the heater array uses one switch (e.g., diode) for every heater in the heater array to provide the ability to independently control each heater in the heater array. The switches increase manufacturing complexity, add cost, and have reliability and lifetime issues.
The present disclosure provides a heater array without switches. The substrate support according to the present disclosure includes only resistive traces as heaters, bus lines connected directly to the heaters, and wired connections to a controller connected to a power source that supplies power to the heaters in the heater array. No switches or switch interconnects for the heaters are needed in the heater array.
More specifically, the heater array according to the present disclosure includes resistive heaters (hereinafter heaters) arranged along X rows of conductors (called X conductors or X bus lines) and Y columns of conductors (called Y conductors or Y bus lines). Every heater in a row is directly connected to a conductor in a row (an X bus line), and every heater in a column is directly connected to a conductor in a column (a Y bus line). The X and Y bus lines do not intersect each other. A selected one of the conductors in the columns (i.e., a Y bus line) is connected to a power supply, and a selected one of the conductors in the rows (i.e., an X bus line) is connected to a reference potential (e.g., ground). Conversely, in some implementations, power is selectively supplied to the X bus lines, and the Y bus lines are selectively grounded.
In the heater array, the highest amount of heat is generated by the heater that is connected to both the selected column and the selected row, which are respectively connected to the power supply and ground. A relatively smaller amount of heat is generated by every other heater on the selected column and the selected row. A still smaller amount of heat is generated by the rest of the heaters in the heater array. Although only one X bus line and only one Y bus line is selected at a time, graded heat is generated throughout the heater array since various current paths are available in the heater array because of the direct connections of the heaters to the X and Y bus lines. Heat patterns generated by selecting different combinations of heaters can be used to create a global heating response with localized control of temperature.
Due to the direct connections of the heaters to the rows and columns of the heater array, the heater array eliminates the need for switches (e.g., diodes), which increases reliability of operation and lifetime, and reduces complexity and cost of manufacturing substrate supports. While a completely localized heater response, which is possible when switches are used, is unavailable, a relatively localized temperature response is achieved due to the coupling between the selected and unselected heaters. These and other features of the present disclosure are described below in detail.
The present disclosure is organized as follows. Initially, examples of substrate processing systems in which the heater array of the present disclosure can be used are shown and described with reference to
The tuning circuit 13 may be directly connected to an inductive coil 16. While the substrate processing system 10 uses a single coil, some substrate processing systems may use a plurality of coils (e.g., inner and outer coils). The tuning circuit 13 tunes an output of the RF source 12 to a desired frequency and/or a desired phase, and matches an impedance of the inductive coil 16.
A dielectric window 24 is arranged along a top side of a processing chamber 28. The processing chamber 28 comprises a substrate support (or pedestal) 30 to support a substrate 34. The substrate support 30 may include an electrostatic chuck (ESC), or a mechanical chuck or other type of chuck. The substrate support 30 comprises a baseplate 32. A ceramic plate 33 is arranged on a top surface of the baseplate 32. A thermal resistance layer 36 may be arranged between the ceramic plate 33 and the baseplate 32. The substrate 34 is arranged on the ceramic plate 33 during processing.
A heater array 35 including a plurality of heaters according to the present disclosure is arranged in the ceramic plate 33 to heat the substrate 34 during processing. For example, the heater array 35 comprises printed resistive traces embedded in the ceramic plate 33 as explained below in detail with reference to
The baseplate 32 further includes a cooling system 38 to cool the substrate support 30. The cooling system 38 uses a fluid supplied by a fluid delivery system 39 to cool the substrate support 30. For example, the cooling system 38 comprises cooling channels through which the fluid from the fluid delivery system 39 is flowed to cool the substrate support 30.
A process gas is supplied to the processing chamber 28, and plasma 40 is generated in the processing chamber 28. The plasma 40 etches an exposed surface of the substrate 34. An RF source 50, a pulsing circuit 51, and a bias matching circuit 52 may be used to bias the substrate support 30 during processing to control ion energy.
A gas delivery system 56 may be used to supply a process gas mixture to the processing chamber 28. The gas delivery system 56 may include process and inert gas sources 57, a gas metering system 58 such as valves and mass flow controllers, and a manifold 59. A gas injector 63 may be arranged at a center of the dielectric window 24 and is used to inject gas mixtures from the gas delivery system 56 into the processing chamber 28. Additionally or alternatively, the gas mixtures may be injected from the side of the processing chamber 28.
A temperature controller 64 may be connected to the heater array 35 and may be used to control the heater array 35 to control a temperature of the substrate support 30 and the substrate 34. The temperature controller 64 controls the heater array 35 as described below in detail with reference to
An exhaust system 65 includes a valve 66 and pump 67 to control pressure in the processing chamber 28 and/or to remove reactants from the processing chamber 28 by purging or evacuation. A controller 70 may be used to control the etching process. The controller 70 controls the components of the substrate processing system 10. The controller 70 monitors system parameters and controls delivery of the gas mixture; striking, maintaining, and extinguishing the plasma; removal of reactants; supply of cooling fluid; and so on. Additionally, the controller 70 may control various aspects of the coil driving circuit 11, the RF source 50, and the bias matching circuit 52, and so on.
The substrate processing system 100 comprises the processing chamber 102 that encloses other components of the substrate processing system 100 and contains RF plasma (if used). The processing chamber 102 comprises an upper electrode 104 and an electrostatic chuck (ESC) 106 or other type of substrate support. During operation, a substrate 108 is arranged on the ESC 106.
For example, the upper electrode 104 may include a gas distribution device 110 such as a showerhead that introduces and distributes process gases into the processing chamber 102. The gas distribution device 110 may include a stem portion including one end connected to a top surface of the processing chamber 102. A base portion of the showerhead is generally cylindrical and extends radially outwardly from an opposite end of the stem portion at a location that is spaced from the top surface of the processing chamber 102. A substrate-facing surface or faceplate of the base portion of the showerhead includes a plurality of outlets or features (e.g., slots or through holes) through which vaporized precursor, process gas, cleaning gas, or purge gas flows.
The ESC 106 comprises a baseplate 112 that acts as a lower electrode. A ceramic plate 114 is arranged on a top surface of the baseplate 112. A thermal resistance layer 116 may be arranged between the ceramic plate 114 and the baseplate 112. The ceramic plate 114 includes a heater array 152 according to the present disclosure to heat the substrate 108. The heater array 152 comprises printed resistive traces embedded in the ceramic plate 114 as explained below in detail with reference to
The baseplate 112 further includes a cooling system 118 to cool the ESC 106. The cooling system 118 uses a fluid supplied by a fluid delivery system 154 to cool the ESC 106. For example, the cooling system 118 comprises cooling channels through which the fluid from the fluid delivery system 154 is flowed to cool the ESC 106.
If plasma is used, an RF generating system (or an RF source) 120 generates and outputs an RF voltage to one of the upper electrode 104 and the lower electrode (e.g., the baseplate 112 of the ESC 106). The other one of the upper electrode 104 and the baseplate 112 may be DC grounded, AC grounded, or floating. For example, the RF generating system 120 may include an RF generator 122 that generates RF power that is fed by a matching and distribution network 124 to the upper electrode 104 or the baseplate 112. In other examples, while not shown, the plasma may be generated inductively or remotely and then supplied to the processing chamber 102.
A gas delivery system 130 includes one or more gas sources 132-1, 132-2, ..., and 132-N (collectively gas sources 132), where N is an integer greater than zero. The gas sources 132 are connected by valves 134-1, 134-2, ..., and 134-N (collectively valves 134) and mass flow controllers 136-1, 136-2, ..., and 136-N (collectively mass flow controllers 136) to a manifold 140. A vapor delivery system 142 supplies vaporized precursor to the manifold 140 or another manifold (not shown) that is connected to the processing chamber 102. An output of the manifold 140 is fed to the processing chamber 102. The gas sources 132 may supply process gases, cleaning gases, or purge gases.
A temperature controller 150 may be connected to the heater array 152 and may be used to control the heater array 152 to control a temperature of the ESC 106 and the substrate 108. The temperature controller 150 controls the heater array 152 as described below in detail with reference to
A valve 156 and pump 158 may be used to evacuate reactants from the processing chamber 102. A system controller 160 controls the components of the substrate processing system 100.
In the embodiment depicted in
The heater array 200 includes Y sets of heaters Hxiy1, Hxiy2, and so on that are arranged along Y columns of the heater array 200, where i = 1 to 5; and X sets of heaters Hx1yj, Hx2yj, and so on that are arranged along X rows of the heater array 200, where j=1 to 5. Each of the Y sets of heaters is connected to one of the Y bus lines of the heater array 200. Each of the X sets of heaters is connected to one of the X bus lines of the heater array 300. Specifically, heaters in a column have first terminals connected to the Y bus line in the column and second terminals connected to respective X bus lines in the X rows, and heaters in a row have first terminals connected to respective Y bus lines in the Y columns and second terminals connected the X bus line in the row.
For example, in the Y sets of heaters, the heaters Hxiy1, where i = 1 to 5, have first terminals directly connected to the Y1 bus line and second terminals connected to respective X bus lines via respective switches Sxiy1, where i = 1 to 5; the heaters Hxiy2, where i = 1 to 5, have first terminals directly connected to the Y2 bus lines and second terminals connected to respective X bus lines via respective switches Sxiy2, where i = 1 to 5; and so on.
In the X sets of heaters, the heaters Hx1yj, where j = 1 to 5, have first terminals directly connected to respective Y bus lines and second terminals connected to the X1 bus line via respective switches Sx1yj, where j = 1 to 5; the heaters Hx2yj, have first terminals directly connected to respective Y bus lines and second terminals connected to the X2 bus line via respective switches Sx2yj, where j = 1 to 5; and so on.
The switches Sxiy1, Sxiy2, and so on and the switches Sx1yj, Sx2yj, and so on are collectively called switches Sxy. The number of switches Sxy is equal to the number of heaters Hxy, which is X*Y (i.e., X multiplied by Y).
The Y and X bus lines are respectively connected to a power supply (e.g., a voltage source) and a reference potential (e.g., ground). A controller (e.g., element 64 or 150 shown in
The ceramic plate 260 includes several stacked layers of a ceramic material. A clamping electrode 270 is disposed in a first layer 272, which is the top layer on which a substrate (e.g., element 34 or 108 shown in
While not shown, one or more additional zone heaters (also called primary heaters) may be arranged in the ceramic plate 260. For example, these heaters can be arranged above the heater array 200 and under the clamping electrode 270 (e.g., in the first layer 272). Alternatively, these heaters can be arranged under the heater array 200 (e.g., in a fifth layer 290 of the ceramic plate 260).
The switches Sxy increase manufacturing complexity, add cost, and have reliability and lifetime issues. Instead, the present disclosure provides a substrate support without the switches Sxy as follows.
In the embodiment depicted in
The heater array 300 includes Y sets of heaters Hxiy1, Hxiy2, and so on that are arranged along Y columns of the heater array 300, where i = 1 to 5. The heater array 300 includes X sets of heaters Hx1yj, Hx2yj, and so on that are arranged along X rows of the heater array 300, where j=1 to 5. Each of the Y sets of heaters is directly connected to one of the Y bus lines of the heater array 300. Each of the X sets of heaters is directly connected to one of the X bus lines of the heater array 300.
Specifically, heaters in a column have first terminals directly connected to the Y bus line in the column and second terminals directly connected to respective X bus lines in the X rows, and heaters in a row have first terminals directly connected to respective Y bus lines in the Y columns and second terminals directly connected the X bus line in the row.
For example, in the Y sets of heaters, the heaters Hxiy1, where i = 1 to 5, have first terminals directly connected to the Y1 bus line and second terminals directly connected to respective X bus lines; the heaters Hxiy2, where i = 1 to 5, have first terminals directly connected to the Y2 bus lines and second terminals directly connected to respective X bus lines; and so on.
In the X sets of heaters, the heaters Hx1yj, where j = 1 to 5, have first terminals directly connected to respective Y bus lines and second terminals directly connected the X1 bus line; the heaters Hx2yj, where j = 1 to 5, have first terminals directly connected to respective Y bus lines and second terminals directly connected the X2 bus line; and so on.
The Y and X bus lines are connected to a controller (e.g., element 64 or 150 shown in
The ceramic plate 360 includes several stacked layers of a ceramic material. A clamping electrode 370 is disposed in a first layer 372, which is the top layer on which a substrate (e.g., element 34 or 108 shown in
The second, third, and fourth layers 374, 376, 378 can be arranged in any order. For example, the second layer 374 can be arranged at the bottom of the ceramic plate 360 adjacent to the baseplate 352 (i.e., between the ceramic plate 360 and the baseplate 352). In some implementations, instead of being arranged in the second layer 374 in the ceramic plate 360, the heaters Hxy can be electrically insulated and arranged external to the ceramic plate 360 at the bottom of the ceramic plate 360 adjacent to the baseplate 352 (i.e., between the ceramic plate 360 and the baseplate 352).
The power supply 406 can also supply power to the zone heater 386 shown in
While the row and column selectors 402, 404 are shown as being external to the controller 400, in some implementations, the controller 400 may include the row and column selectors 402, 404. Further, the controller 400 and the row and column selectors 402, 404 are not implemented in the substrate support 350. Instead, the controller 400 and the row and column selectors 402, 404 are located outside the substrate support 350. The X and Y bus lines from the heater array 300 in the substrate support 350 are connected to the row and column selectors 402, 404 in the controller 400.
The heaters other than the heater 450 at the intersection of the selected X and Y bus lines that are also connected to the selected X and Y bus lines are shown by four dotted ovals 452-1 and 452-1 (collectively called the heaters 452) and 454-1 and 454-2 (collectively called the heaters 454). Additional other heaters in the heater array 300 are identified by dotted ovals 460-1, 460-2, 460-3, and 460-4 (collectively heaters 460), and by dotted ovals 462-1, 462-2, 462-3, and 462-4 (collectively heaters 462).
For example, in
Due to these current paths, the heat generated by the heaters 460 and 462 is approximately the same. The heat generated by the heaters 452 and 454 is greater than the heat generated by the heaters 460 and 462 and is less than the heat generated by the heater 450.
For example,
As shown in the example in
For example,
In
Accordingly, heater arrays having different number of heaters, different number of bus lines, and different configurations can be implemented in substrate supports depending on application and temperature profile requirements. For example, in some implementations, a heater array (e.g., the heater array 300, 480) including X and Y bus lines need not include X*Y heaters; rather a heater array can include less than or equal to X*Y heaters. Regardless of the number of heaters, the number of bus lines, and the configurations of the heater arrays, the controller 400 can control the heaters in the heater arrays in various sequences as described above to generate desired temperature profiles for processing substrates.
At 502, the method 500 receives a sequence in which to energize the heaters in the heater array to process the substrate. That is, the sequence may include an order in which to select X and Y bus lines of the heater array and supply power to the selected X and Y bus lines of the heater array. For example, the sequence may be based on a desired temperature profile for the substrate being processed. At 504, the method 500 selects a first row and a first column of heaters (i.e., first X and Y bus lines) in the heater array according to the sequence. At 506, the method 500 connects the selected row and column of heaters (i.e., first X and Y bus lines) across a reference potential and a voltage source (e.g., applies a DC voltage across the heaters in the first X and Y bus lines of the selected row and column of heaters).
At 508, the method 500 determines if a predetermined amount of time has elapsed. That is, the method 500 applies the DC voltage across the heaters in the selected X and Y bus lines for the predetermined amount of time. The predetermined amount of time is selected based on the data associated with the sequence. The predetermined amount of time may be the same throughout the method 500 (i.e., for all sequence steps) or may vary each time steps 504, 506, and 508 are performed by the method 500. The method 500 proceeds to step 510 after the predetermined amount of time has elapsed.
At 510, the method 500 determines if the sequence is completed. The method 500 proceeds to step 512 if the sequence is not completed and proceeds to step 516 if the sequence is completed. At 510, the method 500 disconnects the selected row and/or column of heaters (i.e., the selected X and/or Y bus lines) from the reference potential and/or the voltage source, respectively. At 514, the method 500 selects a next row and/or a next column of heaters (i.e., a next X and/or Y bus lines) in the heater array according to the sequence and connects the selected row and/or column of heaters across the reference potential and the voltage source (e.g., applies a DC voltage across the next X and/or Y bus lines of the selected row and/or column of heaters). The method 500 returns to step 508.
At 510, if the method 500 determines that the sequence is completed, the method 500 proceeds to step 516. At 516, the method 500 determines whether to repeat the same sequence or to obtain a new sequence in which to energize the heaters in the heater array for subsequent processing of the substrate. Alternatively, the method 500 can also end after completing the sequence. The method 500 returns to step 504 if the same sequence is to be repeated. The method 500 returns to step 502 if a new sequence is to be obtained for subsequent processing of the substrate.
The foregoing description is merely illustrative in nature and is not intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims.
It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure. Further, although each of the embodiments is described above as having certain features, any one or more of those features described with respect to any embodiment of the disclosure can be implemented in and/or combined with features of any of the other embodiments, even if that combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and permutations of one or more embodiments with one another are within the scope of this disclosure.
Spatial and functional relationships between elements (for example, between modules, circuit elements, semiconductor layers, etc.) are described using various terms, including “connected,” “engaged,” “coupled,” “adjacent,” “next to,” “on top of,” “above,” “below,” and “disposed.” Unless explicitly described as being “direct,” when a relationship between first and second elements is described in the above disclosure, that relationship can be a direct relationship where no other intervening elements are present between the first and second elements, but can also be an indirect relationship where one or more intervening elements are present (either spatially or functionally) between the first and second elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A OR B OR C), using a non-exclusive logical OR, and should not be construed to mean “at least one of A, at least one of B, and at least one of C.”
In some implementations, a controller is part of a system, which may be part of the above-described examples. Such systems can comprise semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems.
The controller, depending on the processing requirements and/or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system.
Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software).
Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.
The controller, in some implementations, may be a part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.
In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control.
Thus as described above, the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.
Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers.
As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.
This application claims the benefit of U.S. Provisional Application No. 63/063,700, filed on Aug. 10, 2020. The entire disclosure of the application referenced above is incorporated herein by reference.
Filing Document | Filing Date | Country | Kind |
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PCT/US2021/044122 | 8/2/2021 | WO |
Number | Date | Country | |
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63063700 | Aug 2020 | US |