Patent Application
20170345780
This disclosure relates generally to the field of semiconductor devices and the methods of fabrication thereof, and more particularly, without limitation, to a surface conditioning, modification and/or treatment methodology in a semiconductor device.
Without limitation, the following is provided in the context of fabricating bond pads (sometimes also referred to as contact pads) by way of illustration. Connecting microelectronic components, in particular semiconductor chips or microelectromechanical components or systems (MEMS), etc. requires a process that can provide a low cost yet rugged, robust and reliable method of interconnection. Wire bonding is generally considered the most cost-effective and flexible interconnect technology, and is used to assemble the vast majority of semiconductor packages. It is the primary method of making interconnections between the integrated circuit (IC) and the package leadframe (LF) or printed circuit board (PCB) substrate during semiconductor device assembly. However, successful wire bonding is critically dependent upon the surface finish of both the component's bond pads and the substrate.
It is known that semiconductor devices may include metal layers forming bond pads that may suffer from detrimental processes such as oxidation, corrosion, etc., as well as from processes that lack sufficient cleanliness in certain aspects. One skilled in the art will appreciate that semiconductor devices, bonding connectors and processes for manufacturing these components constantly have to be improved with respect to achieving high performance, high reliability and lowering manufacturing costs.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to a more detailed description that is presented later.
In one aspect, an embodiment of a method operative in fabricating a semiconductor device is disclosed. The claimed method comprises, inter alia, creating a plurality of recessed features in a process layer of the semiconductor device, wherein the recessed features include a nickel-palladium (Ni—Pd) surface that can contain residual materials generated in creating the recessed features; and removing the residual materials from the Ni—Pd surfaces of the recessed features by subjecting or exposing the semiconductor device to a plasma of reactive ion species for a specific duration. In an example embodiment, the plasma may be formed of O2-based plasma chemistry.
In another aspect, an embodiment of a bond pad structure for an integrated circuit, die or chip formed on a wafer or portion thereof is disclosed. The bond pad structure comprises, inter alia, a first layer primarily comprising copper, having connections to underlying circuitry, the first layer being at least partially overlain by a patterned protective overcoat (PO) layer, thereby leaving an exposed portion. A nickel-palladium (Ni—Pd) diffusion barrier layer is deposited over the exposed portion of the first layer, the Ni—Pd diffusion barrier layer operating to prevent the copper from reacting with materials which are bonded to the bond pad structure, wherein the Ni—Pd diffusion barrier layer is treated by a plasma ashing process for improved residue removal.
In a still further aspect, another embodiment of a bond pad structure for an integrated circuit comprises, inter alia, a first layer primarily comprising copper and having connections to underlying circuitry that is at least partially overlain by a patterned PO layer, thereby leaving an exposed portion. A diffusion barrier layer is overlain the first layer, the diffusion barrier layer having a thickness achieved by applying a chemical-mechanical polishing (CMP) process, wherein the diffusion barrier layer is treated by a plasma ashing process for improved residue removal, whereby CMP's residual particulate matter or other byproducts are removed by micro-incineration.
In an example embodiment, a diffusion barrier metal layer may be deposited using one of a vapor deposition process, a galvanic plating process and an electroless plating process, and subsequently polished off by a CMP process to remove excessive material, followed by a plasma ashing process for improved residue removal and surface conditioning. In still further embodiments, surface conditioning and material modification of the present invention may be applied to topside metallization process layers, backside metallization process layers, or both, and other process layers having recessed features created by CMP processes and the like.
In yet another aspect, an embodiment of a semiconductor fabrication method is disclosed. The claimed embodiment comprises, inter alia, forming a metallization layer including bond pad areas of a semiconductor device; forming a protective overcoat (PO) firm overlying the metallization layer; selectively etching the PO layer to expose the bond pad areas, thereby generating a patterned PO layer having recessed features; applying a diffusion barrier composition material on top of the patterned PO layer to fill the recessed features; polishing off the diffusion barrier composition material (e.g., excess material) to expose the recessed features having a diffusion barrier composition material layer with a selective thickness over the bond pad areas; and applying a plasma ash process to incinerate residual materials left in the recessed features after the diffusion barrier composition material has been polished off.
Embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the Figures of the accompanying drawings in which like references indicate similar elements. It should be noted that different references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references may mean at least one. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
The accompanying drawings are incorporated into and form a part of the specification to illustrate one or more exemplary embodiments of the present disclosure. Various advantages and features of the disclosure will be understood from the following Detailed Description taken in connection with the appended claims and with reference to the attached drawing Figures in which:
The present invention is described with reference to the attached Figures wherein like reference numerals are generally utilized to refer to like elements throughout. The Figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
In the following description, reference may be made to the accompanying drawings wherein certain directional terminology, such as, e.g., “upper”, “lower”, “top”, “bottom”, “left-hand”, “right-hand”, “front side”, “backside”, “vertical”, “horizontal”, etc., may be used with reference to the orientation of the Figures or illustrative elements thereof being described. Since components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is understood that further embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The features of the various exemplary embodiments described herein may be combined with each other unless specifically noted otherwise.
As employed in this specification, the terms “coupled”, “electrically coupled”, “connected” or “electrically connected” are not meant to mean that elements must be directly coupled or connected together. Intervening elements may be provided between the “coupled”, “electrically coupled”, “connected” or “electrically connected” elements.
Example semiconductor devices described below may include or formed of a semiconductor material like Si, SiC, SiGe, GaAs or an organic semiconductor material. The semiconductor material may be embodied as a semiconductor wafer or a semiconductor chip containing any type of ICs, for example including but not limited to, digital, analog, mixed-signal, or power semiconductor chips. An example semiconductor chip or die may include integrated circuits, control circuits to control integrated circuits, microprocessors and/or microelectromechanical components or systems (MEMS), inter alia. The semiconductor chip may further include inorganic and/or organic materials that are not semiconductors, for example, insulators such as dielectric layers, plastics or metals, etc.
Examples of semiconductor devices fabricated using surface conditioning, modification or other treatments described below may include a plurality of bonding pads (also referred to as contact pads or bond pads) which may be made of or include a metal, e.g., copper, aluminum, etc., and may further comprise one or more layers of diffusion barrier layers. The contact pads may be configured to provide electrical connections between an integrated circuit of the semiconductor device and respective connecting elements connected to the contact pads. Possibilities to contact the contact pad include soldering, wire bonding, clip bonding, flip chip mounting and probe needles, among others. The connecting element may thus be embodied as a bonding wire or a bonding clip in some example embodiments.
Example bonding wires that may be bonded to contact pads that have had surface conditioning processes described below may include a wire core which may include a metal or a metal alloy, e.g., a copper or a copper alloy. The wire diameter may have a thickness ranging from less than a micron to several hundred microns, depending on application. In an example embodiment, wire diameters may be between 15 to 250 microns depending on a particular application. The wire core may have a substantially circular cross section such that term “thickness” of the wire core may refer to the diameter of the wire core.
Example bonding wires that may be bonded to contact pads that have had surface conditioning processes described below may further include a coating material arranged over the wire core. For example, an embodiment may include a coating material comprising one of niobium, tantalum, an alloy comprising niobium and tantalum, palladium-coated materials (e.g., Pd-coated copper or PCC), and the like. The properties of some of the coating materials (physical and chemical properties, thickness, etc.) may correspond to the properties of similar layers set forth herein.
The bonding wires or materials that may be bonded to contact pads of the present invention may include a passivation layer, for example, an oxide layer. In this connection, the term “passivation” may refer to avoiding or inhibiting oxidation and corrosion of a material sheathed by or arranged underneath the passivation layer. For example, the passivation layer may be generated via a spontaneous formation of a hard non-reactive surface film (spontaneous passivation). The passivation layer may have a thickness between 1 and 10 nm, in particular, between 4 and 8 nm in some example embodiments.
Referring now to the drawings and more particularly to
In an embodiment of the present invention, NiPd-based surface finish/metallization may be provided in combination with bond pad integration involving bond over active circuitry (BOAC) arrangements that are advantageous for carrying higher current densities by upper level metals. Typically, BOAC arrangements are provided with extra thick Cu routing having sufficient dimensions capable of higher current that is not possible with Al bond pads. NiPd-based compositions are particularly advantageous in enabling bonding to BOAC-type bond pad structures without relying on intermetallic formation and avoiding copper oxidation issues, but instead relying on mutually miscibility bonding. Whereas Pd may be added to protect the Ni (e.g., from oxidation), Pd can be reactive and catalytic in some instances, however. To help alleviate the reactivity or catalytic nature of the Pd surface and thus enable improved bonding, a plasma ashing process in accordance with the teachings of the may be implemented, with the additional advantages of surface conditioning as set forth herein.
It should be appreciated that while aluminum bond pads have been the standard in the semiconductor industry for decades, more and more chip manufacturers are looking to copper as device sizes shrink because of improved RC characteristics, among others. One of the issues encountered with copper metallization, however, is that it is not optimal for bonding directly. Copper, unlike aluminum, does not form a self-passivating oxide. When aluminum or gold wires are bonded to the copper, intermetallics are formed which are more resistive and which expand volumetrically, causing cracks and lowering reliability. One solution to this has been to form a barrier layer over the copper bond pad, which barrier layer may comprise multiple sub-layers, topped by a topmost layer that provides suitable physiochemical and electrical properties, allowing it to be bonded to a variety of bonding connector materials using known technologies. Accordingly, in one embodiment, a barrier metal composition layer (also referred to as a diffusion barrier or metal passivation layer) may be formed overlying the patterned PO layer (block 208), wherein a variety of metals, metallic compositions (e.g., including metal oxides, metal nitrides, etc.) may be applied using several techniques such as, e.g., galvanic electroplating, electroless plating, physical vapor deposition (PVD), sputter deposition, and the like. Example metals and metallic compositions or alloys that may be used for forming a diffusion barrier layer structure for the bond pads may include but not limited to: tantalum nitride (TaN), nickel (Ni), palladium (Pd), titanium nitride (TiN), and titanium (Ti), tungsten (W), titanium-tungsten, Cu—Ti, NiPd(Au), tungsten nitride (W—N), titanium silicon nitride (Ti—Si—N), tantalum silicon nitride (Ta—Si—N), cobalt (Co), chromium (Cr), molybdenum (Mo), etc. as well as any combinations thereof in various stoichiometric ratios, that operates to prevent intermetallic formation by impeding the up-diffusion of copper from the bond pads.
In general, a suitable diffusion barrier metal or composition may be deposited or otherwise applied over the wafer, overfilling the various recessed features patterned into the PO layer. Thereafter, a removal process may be applied, e.g., a chemical-mechanical polish (CMP) process, to remove excess diffusion barrier material, thereby leaving/forming a diffusion barrier layer or cap of certain desired thickness over the copper bond pads.
In one example implementation, a CMP process may use an abrasive/corrosive chemical slurry (commonly a colloid) in conjunction with a polishing pad and retaining ring, typically of a greater diameter than the wafer. The pad and wafer are pressed together by a dynamic polishing head and held in place by a plastic retaining ring. The dynamic polishing head may be rotated with specific axial geometry to remove the excess barrier metal composition and expose the recessed features (e.g., trenches, windows, openings for the bond pads, scribe seal, test pads, scribe marks, etc.), as set forth at block 210. The slurry for the CMP process may contain oxidizing or hydroxylating agents as well as mechanical polishing components for metals which may be not readily oxidized under normal conditions. In order to minimize undesired scratches or other deformities of the underlying copper or dielectric layers, a combination of buffers and soft poromeric pads may be used in one example implementation. Alternatively or additionally, organic buffers may be used in still further embodiments.
A wet cleaning process may be employed afterwards in order to remove the residual slurry byproducts and other materials of a CMP process. However, it should be appreciated that such wet processes are not efficient enough in removing the residual matter from the patterned PO layer, thereby negatively impacting the bond pad surface conditioning, e.g., increased defect counts and particulates as well as higher contact resistance to external connectors (e.g., wire-bonding connectors). Furthermore, the residual matter in narrower or smaller features (e.g., scribe seal, small test pads and miscellaneous scribe marks, etc.) may get packed with the slurry materials that are even more resistant to cleaning because of compaction upon drying. In accordance with the teachings herein, a plasma ash process may be applied (block 212) in addition to or in lieu of a wet process in order to improve the surface conditioning of the bond pads as well as clean the narrower features, wherein a suitable plasma chemistry may be designed with appropriate processing parameters, e.g., temperature profile, ranges of time, RF excitation frequencies and energies, pressure ranges, and the like, to micro-incinerate the residual matter in oxidative and/or reductive reactant species. For example, both low and medium temperatures as well as high temperature plasma environments may be employed, although high temperature ashing (e.g., 250° C. to 350° C.) may need to be followed by annealing of wafers. A typical low temperature plasma ashing process (e.g., 50° C. to 150° C.) of the present invention may not charge the wafer to such an extent that it requires annealing thereafter. In an example application, the plasma ash process of the present invention may therefore be practiced using a wide range of temperatures, from approximately 50° C. to 350° C.
In one example implementation, a plasma ashing process may be accomplished through the use of a low pressure, RF-induced gaseous discharge. The semiconductor wafer (or a plurality of wafers, if a batch process is deployed) may be loaded into a reaction chamber that is evacuated to a vacuum pressure to 0.1 to 0.2 torr by a mechanical vacuum pump. A carrier gas may be introduced into the chamber, raising the chamber pressure to 0.3 to 1.2 torr, depending on the application and chemistry. RF power (e.g., by way of a strong electromagnetic field at 13 to 15 MHz) may be applied around the chamber at a few hundred watts (e.g., 400 to 900 W), which dissociates the carrier gas molecules into chemically active ions and molecules (e.g., reactive ions or species such as monoatomic oxygen, etc. in certain plasma chemistries) by ionization, excitation and dissociation of the carrier molecules/atoms. Micro-incineration of the residual matter may typically result in common combustion products such as carbon oxides and water vapor at least with respect to organic moieties.
Several types of plasma ashers may be implemented in accordance with the teachings herein for purposes of surface conditioning, modification and treatment in semiconductor fabrication, which may vary considerably in terms of excitation frequency (e.g., 5 KHz to 5 GHz), operating pressure (e.g., 1 millibar to 1 atm), electrode arrangement, etc. In addition to barrel reactors, parallel plate reactors that are isotropic or anisotropic may also be employed. In a downstream plasma arrangement, reactive species may be generated at one place and carried downstream to a place or chamber or enclosure that houses the semiconductor wafer(s). Also, plasma ashers may be based on inductively coupled RF plasmas, capacitively coupled RF plasmas, electron cyclotron resonance plasmas, etc., wherein carrier gas chemistries may comprise or based on one or more of: O2, Ar, H2, He, N2, C2H4, CH4, C2H2, CF4, SF6, C2F6, CCl4, O2+H2N2, C2Cl6, SiF4, and CO, etc.
Set forth below are further details with respect to one or more processes, sub-processes or steps described hereinabove, taking reference to additional example implementations that may be practiced in an embodiment of the present invention.
Turning to
In another fabrication, a device having protective overcoat layers or silicon dioxide, silicon oxynitride, and silicon dioxide differs from that described above in that oxygen may be introduced along with nitrogen, silane, and ammonia curing the deposition process for the second layer (e.g., layer 310). The processes for silicon oxynitride are known and used throughout the industry for several types of IC fabrication. Processes for the first and third layers of the overcoat 350 may remain unchanged from that described above. Fabrication of protective overcoat of yet another embodiment including a layer of silicon dioxide, silicon carbide, and silicon dioxide differs from the embodiment of
Each of the processes for deposition and patterning is well known throughout the semiconductor industry, and the equipment is widely used. The combined successive processes form a unique PO structure having enhanced adhesion to polymers used in IC package assembly, as well as good adhesion between the film layers, and having minimal stresses on the circuits, thereby providing a strong, low defect, chip passivation. It should be appreciated that PECVD processing of successive overcoat layers eliminates excessive wafer handling by sequentially depositing layered films in a single chamber. Processes employing plasma enhanced chemical vapor deposition provide clean, uncontaminated surfaces between the layers as a function of the atmospheric control within the chamber, thus facilitating adhesion between the multiple layers. Further, PECVD optimizes process cycle time by successive depositions without handling, and by a single photopatterning step to etch openings. The completely inorganic overcoat set forth above for purposes of the present invention not only provides device performance advantages of enhanced adhesion to packaging polymers, but also has very high temperature stability, in excess of 450° C., and has improved thermal conductivity as compared to existing PO technology. In particular the embodiment having a silicon carbide second or barrier layer provides good thermal conductivity, and is applicable to high power circuits.
In one embodiment, exemplary process flow of
In another embodiment, a CuTix/TiN combination may be provided as the diffusion barrier layer. In this embodiment, after deposition of titanium, the semiconductor chip or wafer may be exposed to an ambient which contains either nitrogen or ammonia. During the anneal, the upper surface of the titanium will react with the nitrogen present to form a layer of TiN 410 while the lower surface of the titanium reacts with the copper to form CuTix 408. After the unreacted titanium is removed from the surface of the chip,
Yet another embodiment may involve deposition of TiN for passivation and diffusion barrier. Here, a layer of TiN 412 is deposited over the chip, overfilling the holes through the PO 406. A CMP step removes excess material outside of the holes, giving rise to the structure shown in
Turning now to
In one example process, the residual materials comprise one or more of: quaternary ammonium ions (N(CxHy)4 ions), aryl ester, dioctyl phalate (DOP), Pd(NH3)x, bromine, benzotriazole (BTA), PdO, sodium lauryl sulfate, and other detergent compounds, as well as other organic and/or inorganic compounds or compositions. A plasma ash treatment, as shown by arrows 524 may involve any type of plasma ashing processes, chemistries, process parameters, reactor types, and the like, described hereinabove, with suitable optimizations or customizations depending on the particular semiconductor product and fabrication process. In certain example embodiments, the inventors of the present invention have used O2-based ashing for durations of 150 s to 250 s for main ash, with significant improvement in physical and chemical properties as well as electric/parametric data in test wafer splits.
Based on the foregoing Detailed Description, one skilled in the art will appreciate that example embodiments relating to surface conditioning and material modification advantageously provide improved metallurgical properties as well as enhanced device performance. In the context of the present patent application, it should be understood that “material modification” in an example embodiment may comprises process steps relating to removal/incineration, using a O2 (or other) dry ash, of any foreign/unwanted residual matter or impurities left behind in the wake of a CMP process applied after the diffusion barrier metal deposition, thereby altering the bond pad contact surface, e.g., its electrical properties, adhesion properties, etc. There may also be chemical altering of the barrier metal composition(s) (e.g., where O2 ash is implemented, a metal oxide may be formed). Further, as oxidative ashing can also oxidize a topside metal of a diffusion barrier, e.g., Ni, Pd, etc., beneficial effects may include reduced corrosion in topside acid tests (e.g., more resistant to damaging acids such as nitric acid used in further downstream steps). As plasma treatment processes are generally more benign than wet clean processes, it is envisaged that overall fabrication process flow of a semiconductor foundry is also enhanced.
Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. None of the above Detailed Description should be read as implying that any particular component, element, step, act, or function is essential such that it must be included in the scope of the claims. Reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described embodiments that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Accordingly, those skilled in the art will recognize that the exemplary embodiments described herein can be practiced with various modifications and alterations within the spirit and scope of the claims appended below.
