This invention relates to a susceptor for use in a chemical vapor deposition process, and more particularly to a susceptor for supporting a single semiconductor wafer during a chemical vapor deposition process.
Semiconductor wafers may be subjected to a chemical vapor deposition process such as an epitaxial deposition process to grow a thin layer of silicon on the front surface of the wafer. This process allows devices to be fabricated directly on a high quality epitaxial layer. Conventional epitaxial deposition processes are disclosed in U.S. Pat. Nos. 5,904,769 and 5,769,942, which are incorporated herein by reference.
Prior to epitaxial deposition, the semiconductor wafer is loaded into a deposition chamber and lowered onto a susceptor. After the wafer is lowered onto the susceptor, the epitaxial deposition process begins by introducing a cleaning gas, such as hydrogen or a hydrogen and hydrochloric acid mixture, to a front surface of the wafer (i.e., a surface facing away from the susceptor) to pre-heat and clean the front surface of the wafer. The cleaning gas removes native oxide from the front surface, permitting the epitaxial silicon layer to grow continuously and evenly on the surface during a subsequent step of the deposition process. The epitaxial deposition process continues by introducing a vaporous silicon source gas, such as silane or a chlorinated silane, to the front surface of the wafer to deposit and grow an epitaxial layer of silicon on the front surface. A back surface opposite the front surface of the susceptor may be simultaneously subjected to hydrogen gas. The susceptor, which supports the semiconductor wafer in the deposition chamber during the epitaxial deposition, is rotated during the process to ensure the epitaxial layer grows evenly. Prior art susceptors used in epitaxial growth processes are described in U.S. Pat. Nos. 6,652,650; 6,596,095; and 6,444,027, all of which are incorporated herein by reference.
A common susceptor design includes a disk having a recess with a concave floor. This shape allows the wafer to contact the susceptor at its edge while the remainder of the wafer does not contact the susceptor. If the semiconductor wafer contacts the susceptor at a point other than at its edge, defects can occur at these contact points if the wafer rests on a silicon carbide coating on the susceptor. These defects may lead to front surface dislocations and slip and have the potential to cause device failure.
Applicants have discovered that portions of the wafer other than those the wafer edge can contact the susceptor shortly after the wafer is loaded onto the susceptor. The semiconductor wafer is typically near ambient temperature when it is loaded on the susceptor. In contrast, the susceptor is at a temperature between about 500° C. and about 1000° C. when the wafer is loaded on the susceptor. The temperature difference between the wafer and the susceptor causes the wafer to heat rapidly and bow. The bowing can cause the back surface of the wafer to contact the susceptor, causing defects at the contact points, especially near the center of the wafer.
One approach to prevent wafer back surface damage is to use a susceptor having a more concave floor. This shape increases the distance between the back surface of the wafer and the susceptor. However, it has been discovered that increasing the concavity of the floor causes an increase in wafer slip locations at the wafer edge. Because the mass of the susceptor is significantly larger than the mass of the semiconductor wafer, the wafer temperature generally increases uniformly across the wafer when loaded on the susceptor. However, if the depth of the center of the recess is significantly greater than the depth toward the edge of the recess, radial temperature gradients can form across the wafer. These temperature gradients can result in slip and dislocations in the wafer, especially at the wafer edge.
Another problem presented by conventional susceptors is that susceptors take a long time to heat up and cool down causing increased processing time. Further, because conventional susceptors are solid beneath the entire wafer, they block hydrogen from reaching the wafer back surface to remove native oxide and block outdiffused dopant from the wafer back surface from escaping.
Thus, a need exits for susceptors that reduce or eliminate wafer back surface defects and minimize occurrence of slip dislocations in the wafer. Further, there is a need for a susceptor that reduces processing time by allowing the susceptor to heat up and cool down faster, that allows hydrogen to reach the wafer back surface and that allows outdiffused dopant to escape from the back surface of the wafer.
One aspect of the present invention is directed to a susceptor for supporting a semiconductor wafer in a heated chamber having an interior space. The wafer has a front surface, a back surface opposite the front surface and a circumferential side extending around the front surface and the back surface. The susceptor is sized and shaped for receipt within the interior space of the chamber and for supporting the semiconductor wafer. The susceptor comprises a body having an upper surface and a lower surface opposite the upper surface. Further, the susceptor includes a recess extending downward from the upper surface into the body along an imaginary central axis. The recess is sized and shaped for receiving the semiconductor wafer therein. In addition, the susceptor comprises a plurality of lift pin openings extending through the body from the recess to the lower surface. Each of the plurality of the lift pin openings is sized for accepting lift pins to selectively lift and lower the wafer with respect to the recess. Moreover, the susceptor includes a central opening extending through the body along the central axis from the recess to the lower surface.
Another aspect of the present invention is directed to a susceptor for supporting a semiconductor wafer in a heated chamber having an interior space. The wafer has a front surface, a back surface opposite the front surface and a circumferential side extending around the front surface and the back surface. The susceptor is sized and shaped for receipt within the interior space of the chamber and for supporting the semiconductor wafer. The susceptor comprises a body having an upper surface and a lower surface opposite the upper surface. Further, the susceptor includes a recess extending downward from the upper surface into the body along an imaginary central axis. The recess includes a wafer-engaging face sized and shaped for receiving the semiconductor wafer thereon. The susceptor also has a central opening extending through the body along the central axis from the recess to the lower surface.
In yet another aspect, the present invention includes a susceptor for supporting a semiconductor wafer in a heated chamber having an interior space. The wafer has a front surface, a back surface and a circumferential edge. The susceptor is sized and shaped for supporting the semiconductor wafer within the interior space of the chamber. The susceptor comprises an upper surface and a first recess extending downward from the upper surface. The first recess is adapted to receive the semiconductor wafer. The first recess includes a generally annular first wall and a first ledge extending from the first wall toward a center of the recess. The first ledge has an outer perimeter and an inner perimeter. The first ledge has a downward slope from the outer perimeter to the inner perimeter to facilitate supporting the wafer. The susceptor also comprises a second recess extending downward from the first recess. The second recess includes a generally annular second wall and a second ledge extending inward from the second wall/Further, the susceptor includes a third recess extending downward from the second recess. The third recess includes a generally annular third wall and a floor extending inward from the third wall. The first, second and third recesses have a common central axis.
Still a further aspect of the present invention includes a susceptor for supporting a semiconductor wafer in a chamber having an interior space, a gas inlet for directing process gas to flow into the interior space of the chamber and a gas outlet through which process gas is exhausted from the interior space of the chamber. The wafer has a front surface, a back surface and a circumferential edge. The susceptor is sized and shaped for supporting the semiconductor wafer within the interior space of the chamber. The susceptor comprises an upper surface and a first recess extending downward from the upper surface. The first recess is adapted to receive the semiconductor wafer. Further, the first recess includes a generally annular first wall and a first ledge extending from the first wall toward a center of the recess. The first ledge has an outer perimeter and an inner perimeter. In addition, the susceptor comprises a second recess extending downward from the first recess. The second recess includes a generally annular second wall and a second ledge extending inward from the second wall. Still further, the susceptor includes a third recess extending downward from the second recess. The third recess includes a generally annular third wall and a floor extending inward from the third wall. The distance between the back surface of the wafer and the floor of the third recess is between about 0.005 inches and about 0.030 inches to inhibit contact of the wafer with the susceptor except adjacent the edge of the wafer as the wafer warps during heating.
The present invention also includes a susceptor for supporting a semiconductor wafer in a chamber having an interior space, a gas inlet for directing process gas to flow into the interior space of the chamber and a gas outlet through which process gas is exhausted from the interior space of the chamber. The wafer has a front surface, a back surface and a circumferential edge. The susceptor is sized and shaped for supporting the semiconductor wafer within the interior space of the chamber. Further, the susceptor comprises an upper surface and a wafer-receiving recess extending downward from the upper surface. The recess includes a ledge for supporting the wafer. Still further, the susceptor comprises a central recess coaxial with the wafer-receiving recess and extending deeper into the susceptor than the wafer-receiving recess. The ratio of the surface area of the wafer-receiving recess to the surface area of the central recess is at least about 13 to about 1 to minimize slip.
Various refinements exist of the features noted in relation to the above-mentioned aspects of the present invention. Further features may also be incorporated in the above-mentioned aspects of the present invention as well. These refinements and additional features may exist individually or in any combination. For instance, various features discussed below in relation to any of the illustrated embodiments of the present invention may be incorporated into any of the above-described aspects of the present invention, alone or in any combination.
Corresponding reference characters indicate corresponding parts throughout the drawings.
Referring now to the drawings, and in particular
The susceptor 10 includes a body, generally designated by 20, having a circular shape surrounding an imaginary central axis 22. Further, the body 20 includes an upper surface 24 and a lower surface 26. A first or outer recess, generally designated by 30, extends downward into the body 20 from the upper surface 24. The first recess 30 includes a generally cylindrical wall 32 and a face 34 extending inward from a lower end of the wall 32. The face 34 also slopes downward from the wall 32 toward the central axis 22 of the body 20. The face 34 supports the wafer 12. As shown in
As further shown in
A third or inner recess 50 extends downward into the body 10 from the second recess 40. The third recess 50 includes a cylindrical wall 52 and a floor 54 extending inward from the wall to the central axis 22. According to one embodiment, the height of the wall 52 is about 0.003 inch (0.08 mm). As will be appreciated by those skilled in the art, the third recess 50 prevents the back surface 16 of the wafer 12 near the center of the wafer from contacting the susceptor 10 when the wafer bows downward due to thermal gradients as shown in
It has been found that wafers supported on susceptors in which a vertical distance between the bottom of the second wall 42 and the top of the third wall 52 is greater than about 0.010 inch (0.25 mm) typically have an unacceptable amount of wafer slip dislocations at the wafer edge. Thus, according to one embodiment, the vertical distance between the bottom of the second wall 42 and the top of the third wall 52 is not greater than about 0.007 inch (0.18 mm). According to another embodiment, this distance is not greater than about 0.005 inch (0.10 mm).
According to a further embodiment, the distance between the back surface 16 of the unbowed wafer 12 and the floor 54 of the third recess 50 is between about 0.005 inch (0.13 mm) and about 0.030 inch (0.76 mm). If the distance between the wafer 12 and the floor 54 is at least about 0.005 inch (0.13 mm), wafers without surface damage near the center of the back surface 16 wafer may be produced. If the distance between the wafer 12 and the floor 54 is less than about 0.030 inch (0.76 mm), wafers without a significant number of slip dislocations may be produced. According to another embodiment, the distance between the back surface 16 of the unbowed wafer 12 and the floor 54 of the third recess 50 is between about 0.008 inch (0.20 mm) and about 0.030 inch (0.76 mm) and in another embodiment this distance is between about 0.010 inch (0.25 mm) and about 0.030 inch (0.76 mm).
The three recesses 30, 40, 50 are generally circular and are centered on the imaginary central axis 22 as shown in
The middle recess 40 should be sufficiently large to prevent contact between the back surface 16 of the wafer 12 and the susceptor 10 during heating of the semiconductor wafer. However, the middle recess 40 should not be so large that more of the susceptor mass is removed than is necessary to prevent contact. The susceptor should enable the wafer temperature to increase uniformly upon loading the wafer 12 on the susceptor 10. Thus, according to one embodiment, the ratio of the surface area of the outer recess 30 to the surface area of the middle recess 40 is at least about 13:1 to minimize wafer slip.
Although the susceptor 10 may have other overall dimensions without departing from the scope of the present invention, in one embodiment the susceptor has an overall diameter of about 14.7 inches and an overall thickness of about 0.15 inch. Further, although the susceptor 10 may be made of other materials without departing from the scope of the present invention, in one embodiment the susceptor is made of silicon carbide coated graphite. The susceptor 10 may have a plurality of holes extending from the upper surface 14 to the lower surface 16 as shown and described in U.S. Pat. Nos. 6,652,650 and 6,444,027.
The susceptor 10 described above may be used as part of an apparatus for chemical vapor deposition processes such as an epitaxial deposition process. Referring now to
During the epitaxial deposition process, an epitaxial silicon layer grows on the front surface 14 of the semiconductor wafer 12. The wafer 12 is introduced into the chamber 62 and centered on the face 34 of the susceptor 10. The wafer 12 bows as it heats to the temperature of the susceptor 10. First the apparatus performs a pre-heat or cleaning step. A cleaning gas, such as hydrogen or a mixture of hydrogen and hydrochloric acid, is introduced into the chamber 62 at about ambient pressure, at a temperature between about 1000° C. and about 1250° C., and at a flow rate between about five liters per minute and about 100 liters per minute. After a period of time sufficient to remove native oxide layers from both the front and back surfaces of the wafer 12 and to stabilize the temperature in the reaction chamber 62 between about 1000° C. and about 1250° C., a silicon-containing source gas, such as silane or a chlorinated silane, is introduced through the inlet 60 above the front surface 14 of the wafer 12 at a flow rate between about one liter per minute and about fifty liters per minute. The source gas flow continues for a period of time sufficient to grow an epitaxial silicon layer on the front surface 14 of the wafer 12 to a thickness between about 0.1 micrometer and about 200 micrometers. Simultaneously with the source gas being introduced, a purge gas, such as hydrogen, flows through the inlet 72 below the back surface 16 of the wafer 12. The purge gas flow rate is selected so the purge gas contacts the back surface 16 of the semiconductor wafer 12, reduces native oxide, and carries out-diffused dopant atoms from the back surface to an exhaust outlet 74 at a flow rate between about five liters per minute and about 100 liters per minute.
Referring to
As further illustrated in
As shown in
Conventional susceptors heat up and cool down slowly. For example, a conventional susceptor may take as much as 25 seconds to reach a steady state temperature when heated from about 700° C. to about 1150° C. Further, the temperature gradient across a conventional susceptor may exceed 50° C. or more during heating. In contrast, a susceptor 110 as described above heats up and cools down much more quickly. For example, a susceptor may reach steady state in about 10 seconds when heated from about 700° C. to about 1150° C., and the temperature gradient may never exceed 20° C. during heating.
Referring to
When introducing elements of various aspects of the present invention or embodiments thereof, the articles “a”, “an”, “the” and “said” are intended to mean that there are one or more of the elements. The terms “comprising”, “including” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Moreover, the use of “top” and “bottom”, “front” and “rear”, “above” and “below” and variations of these and other terms of orientation is made for convenience, but does not require any particular orientation of the components.
As various changes could be made in the above constructions, methods and products without departing from the scope of the invention, it is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense. Further, all dimensional information set forth herein is exemplary and is not intended to limit the scope of the invention.
This application incorporates U.S. Provisional Patent Application Ser. No. 60/944,910, filed Jun. 19, 2007, by reference.
Number | Date | Country | |
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60944910 | Jun 2007 | US |